BORA SOM/BORA Hardware

BORA SOM HW Manual

BORA TOP view BORA Block diagram Processor and memory subsystem Hardware versioning and tracking BORA SOM P/N composition BORA SOM RFQ Request For Quotation

Customers are strongly recommended to register their kits. Registration grants access to reserved material such as source code and additional documentation. To register the kit, please send an email to helpdesk@dave.eu, providing the kit P/N and S/N. [link_TBD BORA Hw Manual] PDF Manuals are available only on the latest version. Checkout the pages' history on wiki for previous releases or contact helpdesk@dave.eu

Connectors and Pinout		Power and Reset		Peripherals		Electrical, Thermal and Mechanical Features
Connectors and Pinout Table SOM J1 ODD pins declaration SOM J1 EVEN pins declaration SOM J2 ODD pins declaration SOM J2 EVEN pins declaration SOM J3 ODD pins declaration SOM J3 EVEN pins declaration		Power Supply Unit (PSU) and recommended power-up sequence Reset scheme and control signals PL initialization signals System boot JTAG		Programmable logic (FPGA) Ethernet SDIO SPI CAN I2C UART USB EEPROM Real Time Clock Watchdog		Operational characteristics Thermal management and heat dissipation Mechanical specifications