BORA SOM/BORA Hardware/Power and Reset/Reset scheme and control signals

History
Issue Date	Notes
2021/10/28	New documentation layout
2022/04/25	Updated USB and ETH PHY reset information

Reset scheme and voltage monitoring

The following picture shows the simplified block diagram of reset scheme and voltage monitoring.

Reset signals

The available reset signals are described in detail in the following sections.

MRST

MRSTn is a de-bounced input for manual reset (for example to connect a push-button). This signal connected to the voltage monitor and is pulled-up to 3.3VIN through a 2.2kOhm resistor.

PORSTn

This is a bidirectonal open-drain signal that is connected to Zynq's PS_POR_B and can be asserted by the following devices:

• a multi-rail voltage monitor that monitors 3.3VIN power rails and all of the rails generated by Bora's PSU. This monitor
  • in case of a power glitch, asserts MEM_WPn signal in order to prevent any spurious write operation on flash memories too. MEM_WPn is 3.3V, push-pull, active low.
  • has a timeout (set through an on-board capacitor) of about 200 ms.
  • provides MRSTn debounced input for manual reset (for example to connect a push-button). This signal is pulled-up to 3.3VIN through a 2.2kOhm resistor.
• a watchdog timer (Maxim MAX6373). For more details please refer to Watchdog section.

PORSTn is pulled-up to 3.3VIN through a 2.2kOhm resistor.

SYS_RSTn

This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.

PS_MIO50_501 (USB PHY reset)

By default, this signal is connected to the on-board USB PHY reset input as depicted in the above figure. This scheme allows complete software control of the PHY hardware reset regardless of the PL status.

For example, this is how the reset signal is handled in BELK 4.1.5:

• U-Boot board_init routine generates a hardware reset pulse. This initializes the component to its default register values.
• Linux kernel does not issue any further hardware reset. If a hardware reset is required upon Linux boot up, the phy-ulpi kernel driver and/or the according device tree properties have to be modified for enabling this feature.

PS_MIO51_501 (Ethernet PHY reset)

By default, this signal is connected to the on-board Ethernet PHY reset input as depicted in the above figure. This scheme allows complete software control of the PHY hardware reset regardless of the PL status.

For example, this is how the reset signal is handled in BELK 4.1.5:

• U-Boot board_init routine generates a hardware reset pulse. This initializes the component to its default register values, which are partly determined by the PHY's strapping pins.
• Upon boot up, the Linux kernel issues a software reset via the BCMR register. If a hardware reset is required instead, the macb kernel driver and/or the related device tree properties have to be modified for enabling this feature.

Pins connection

Pin Name	Bora Pin	Bora Lite Pin
MRST	J2.116	J1.20
PORSTn	J2.114	J1.20 (alternate mount option)
SYS_RSTn	J2.112	J1.18
PS_MIO51_501	J2.106	J1.75
PS_MIO50_501	J2.106	-

Clock scheme

Bora is equipped with three independent active oscillators:

• processor (33.3 MHz)
• ethernet PHY (25 MHz)
• USB PHY (26 MHz)

Generally speaking, no clocks have to be provided by the carrier board.