BORA SOM/BORA Hardware/Peripherals/Programmable logic (FPGA)

History
Issue Date	Notes
2021/08/28	New documentation layout

Programmable logic

The following paragraphs describe in detail the available PL I/O pins and how they are routed to the Bora connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too. For more details about PCB design considerations, please refer to the Advanced routing and carrier board design guidelines article.

The following table reports the I/O banks characteristics:

FPGA Bank	Type	I/O Voltage	Voltage Pins	Notes
Bank 35	High range (HR)	User defined VIO=FPGA_VDDIO_BANK35 1.8 to 3.3V	J1.2 J1.66 J1.67 J1.68
Bank 34	High range (HR)	Fixed VIO=3.3 V	-
Bank 13	High range (HR)	User defined VIO=FPGA_VDDIO_BANK13 1.8 to 3.3V	J3.95 J3.96 J3.97 J3.98 J3.99	Bank 13 is available only with Zynq XC7Z020 part number. Although this bank is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway, either to ground or to an external I/O voltage.

Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where:

• IO indicates a user I/O pin.
• L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair.
• Tn indicates the memory byte group [0-3]
• ZZZ indicates a MRCC, SRCC or DQS pin
• ADi indicates a XADC (analog-to-digital converter) differential auxiliary analog input [0–15].
• # indicates the bank number.

Highlighted rows are related to signals that are used for particular functions into the SOM.

FPGA Bank 34

The following table reports the available pins connected to bank 34:

Pin Name	Conn. Pin	Notes
IO_0_34	J2.69
IO_25_34	J2.67
IO_L10N_T1_34	J2.65
IO_L10P_T1_34	J2.63
IO_L11N_T1_SRCC_34	J2.59
IO_L11P_T1_SRCC_34	J2.57
IO_L12N_T1_MRCC_34	J2.62
IO_L12P_T1_MRCC_34	J2.60
IO_L13N_T2_MRCC_34	N.A.
IO_L13P_T2_MRCC_34	N.A.
IO_L14N_T2_SRCC_34	J2.56
IO_L14P_T2_SRCC_34	J2.54
IO_L15N_T2_DQS_34	J2.47
IO_L15P_T2_DQS_34	J2.45
IO_L16N_T2_34	J2.50
IO_L16P_T2_34	J2.48
IO_L17N_T2_34	J2.46
IO_L17P_T2_34	J2.44
IO_L18N_T2_34	J2.41
IO_L18P_T2_34	J2.39
IO_L19N_T3_VREF_34	J2.37
IO_L19P_T3_34	J2.35	Internally used as CAN_RX
IO_L1N_T0_34	J2.40
IO_L1P_T0_34	J2.38
IO_L20N_T3_34	J2.36
IO_L20P_T3_34	J2.34
IO_L21N_T3_DQS_34	J2.31
IO_L21P_T3_DQS_34	J2.29
IO_L22N_T3_34	J2.27
IO_L22P_T3_34	J2.25
IO_L23N_T3_34	J2.30
IO_L23P_T3_34	J2.28
IO_L24N_T3_34	J2.26
IO_L24P_T3_34	J2.24
IO_L2N_T0_34	J2.21
IO_L2P_T0_34	J2.19
IO_L3N_T0_DQS_34	J2.17
IO_L3P_T0_DQS_PUDC_B_34	J2.15	Internally connected to a 10kΩ pull-up
IO_L4N_T0_34	J2.20
IO_L4P_T0_34	J2.18
IO_L5N_T0_34	J2.16
IO_L5P_T0_34	J2.14
IO_L6N_T0_VREF_34	J2.11
IO_L6P_T0_34	J2.9	Internally used as CAN_TX
IO_L7N_T1_34	J2.10
IO_L7P_T1_34	J2.8
IO_L8N_T1_34	J2.7
IO_L8P_T1_34	J2.5
IO_L9N_T1_DQS_34	J2.6
IO_L9P_T1_DQS_34	J2.4

Regarding power voltage, take into consideration that Bank 34 is fixed at 3.3V.

Routing information

Routing implemented on Bora SoM allows the use of bank 34's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.

Pairs are highlighted with different colors. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohm.

Bora pin name	Individual trace length [mils]	Intra-pair match [mils]	Inter-pair match [mils]	Group name
IO_L1N_T0_34	1751,37	25	300	BANK34 Diff group 1
IO_L1P_T0_34	1749,02	25	300	BANK34 Diff group 1
IO_L2N_T0_34	1625,68	25	300	BANK34 Diff group 1
IO_L2P_T0_34	1624,91	25	300	BANK34 Diff group 1
IO_L4N_T0_34	1581,72	25	300	BANK34 Diff group 1
IO_L4P_T0_34	1582,11	25	300	BANK34 Diff group 1
IO_L5N_T0_34	1769,81	25	300	BANK34 Diff group 1
IO_L5P_T0_34	1776,23	25	300	BANK34 Diff group 1
IO_L7N_T1_34	1566,52	25	300	BANK34 Diff group 1
IO_L7P_T1_34	1569,36	25	300	BANK34 Diff group 1
IO_L9N_T1_DQS_34	1490,25	25	300	BANK34 Diff group 1
IO_L9P_T1_DQS_34	1498,04	25	300	BANK34 Diff group 1
IO_L10N_T1_34	1516,97	25	300	BANK34 Diff group 1
IO_L10P_T1_34	1517,37	25	300	BANK34 Diff group 1
IO_L15N_T2_DQS_34	1610,74	25	300	BANK34 Diff group 1
IO_L15P_T2_DQS_34	1602,81	25	300	BANK34 Diff group 1
IO_L16N_T2_34	1601,55	25	300	BANK34 Diff group 1
IO_L16P_T2_34	1616,03	25	300	BANK34 Diff group 1
IO_L17N_T2_34	1574,33	25	300	BANK34 Diff group 1
IO_L17P_T2_34	1593,38	25	300	BANK34 Diff group 1
IO_L18N_T2_34	1740,11	25	300	BANK34 Diff group 1
IO_L18P_T2_34	1750,54	25	300	BANK34 Diff group 1
IO_L20N_T3_34	1588,01	25	300	BANK34 Diff group 1
IO_L20P_T3_34	1585,53	25	300	BANK34 Diff group 1
IO_L21N_T3_DQS_34	1567,1	25	300	BANK34 Diff group 1
IO_L21P_T3_DQS_34	1570,96	25	300	BANK34 Diff group 1
IO_L22N_T3_34	1619,26	25	300	BANK34 Diff group 1
IO_L22P_T3_34	1622,13	25	300	BANK34 Diff group 1
IO_L23N_T3_34	1769,71	25	300	BANK34 Diff group 1
IO_L23P_T3_34	1775,52	25	300	BANK34 Diff group 1
IO_L24N_T3_34	1772,07	25	300	BANK34 Diff group 1
IO_L24P_T3_34	1774,49	25	300	BANK34 Diff group 1
IO_L11N_T1_SRCC_34	1817,43	10	50	BANK34 xRCC group
IO_L11P_T1_SRCC_34	1823,9	10	50	BANK34 xRCC group
IO_L12N_T1_MRCC_34	1844,2	10	50	BANK34 xRCC group
IO_L12P_T1_MRCC_34	1841,36	10	50	BANK34 xRCC group
IO_L13N_T1_MRCC_34	1811,51	10	50	BANK34 xRCC group
IO_L13P_T1_MRCC_34	1818,58	10	50	BANK34 xRCC group
IO_L14N_T2_SRCC_34	1818,78	10	50	BANK34 xRCC group
IO_L14P_T2_SRCC_34	1822,02	10	50	BANK34 xRCC group

The following table lists other signals that are not explicitly routed as differential pairs. Please note that some of these signals are internally used and thus they may have stubs.

Bora pin name	Trace length [mils]	Stubs due to internal use
IO_0_34	1643,08	yes (total length including stubs: 1900,20 mils)
IO_25_34	1484,09	yes (total length including stubs: 1741,03 mils)
IO_L19N_T3_VREF_34	1880,62	yes (total length including stubs: 1959,35 mils)
IO_L19P_T3_34	1066,01	yes (total length including stubs: 1152,88 mils)
IO_L3N_T0_DQS_34	1050,49	yes (total length including stubs: 1133,5 mils)
IO_L3P_T0_DQS_PUDC_B_34	1201,39	yes (total length including stubs: 1385,82 mils)
IO_L6N_T0_VREF_34	1347,42	no
IO_L6P_T0_34	1583,33	yes (total length including stubs 1698,73: mils)
IO_L8N_T1_34	1518,79	yes (total length including stubs 1730,58: mils)
IO_L8P_T1_34	1212,67	yes (total length including stubs 1435,25: mils)

About power voltage, take into consideration that Bank 34 is fixed at 3.3V.

FPGA Bank 35

The following table reports the available pins connected to bank 35:

Pin Name	Conn. Pin	Notes
IO_0_35	J1.74
IO_25_35	J1.18
IO_L10N_T1_AD11N_35	J1.6
IO_L10P_T1_AD11P_35	J1.5
IO_L11N_T1_SRCC_35	J1.10
IO_L11P_T1_SRCC_35	J1.7
IO_L12N_T1_MRCC_35	J1.27
IO_L12P_T1_MRCC_35	J1.8
IO_L13N_T2_MRCC_35	J1.39
IO_L13P_T2_MRCC_35	J1.40
IO_L14N_T2_AD4N_SRCC_35	J1.36
IO_L14P_T2_AD4P_SRCC_35	J1.34
IO_L15N_T2_DQS_AD12N_35	J1.47
IO_L15P_T2_DQS_AD12P_35	J1.46
IO_L16N_T2_35	J1.44
IO_L16P_T2_35	J1.45
IO_L17N_T2_AD5N_35	J1.37
IO_L17P_T2_AD5P_35	J1.32
IO_L18N_T2_AD13N_35	J1.42
IO_L18P_T2_AD13P_35	J1.43
IO_L19N_T3_VREF_35	J1.64
IO_L19P_T3_35	J1.41
IO_L1N_T0_AD0N_35	J1.53
IO_L1P_T0_AD0P_35	J1.50
IO_L20N_T3_AD6N_35	J1.23
IO_L20P_T3_AD6P_35	J1.21
IO_L21N_T3_DQS_AD14N_35	J1.33
IO_L21P_T3_DQS_AD14P_35	J1.31
IO_L22N_T3_AD7N_35	J1.26
IO_L22P_T3_AD7P_35	J1.25
IO_L23N_T3_35	J1.22
IO_L23P_T3_35	J1.28
IO_L24N_T3_AD15N_35	J1.16
IO_L24P_T3_AD15P_35	J1.20
IO_L2N_T0_AD8N_35	J1.51
IO_L2P_T0_AD8P_35	J1.52
IO_L3N_T0_DQS_AD1N_35	J1.63
IO_L3P_T0_DQS_AD1P_35	J1.61
IO_L4N_T0_35	J1.54
IO_L4P_T0_35	J1.56
IO_L5N_T0_AD9N_35	J1.55
IO_L5P_T0_AD9P_35	J1.57
IO_L6N_T0_VREF_35	J1.62
IO_L6P_T0_35	J1.58
IO_L7N_T1_AD2N_35	J1.11
IO_L7P_T1_AD2P_35	J1.3
IO_L8N_T1_AD10N_35	J1.9
IO_L8P_T1_AD10P_35	J1.12
IO_L9N_T1_DQS_AD3N_35	J1.17
IO_L9P_T1_DQS_AD3P_35	J1.15

On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Regarding power voltage, Bank 35 is configurable and must be powered by carrier board. Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs. For routing details, please refer to PL Bank 35 routing.

Routing information

On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Signals have been grouped in the following classes:

• FDDR_ADDR
• FDDR_CK
• FDDR_BYTE0
• FDDR_BYTE1

Some of them are differential pairs. These kind of signals are highlighted in dark grey in the following sections where, for each signal, detailed information are provided, related to routing rules implemented on Bora SoM and carrier board guidelines.

Following tables indicates general recommended rules for single-ended and differantial pairs on carrier board in terms of impedence and isolation.

Differential pairs:

	Value	UOM
Common Mode impedance typ	55	Ohm
Differential Mode impedance typ	100	Ohm
Isolation	4x	gap

Single-ended signals:

	Value	UOM
Common Mode impedance typ	55	Ohm
Isolation	2x	width

About power voltage, Bank 35 is configurable and must be powered by carrier board.

Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs.

FDDR_ADDR class

Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_ADDR class signals. The picture shows connection scheme and the nomenclature used in the table.

Bora pin name	Group name	Carrier board net name	SoM routing rules and specifications			Carrier board guidelines
			Actual length [mils]	Max length match [mils]	Nominal max length [mils]	AD_A2 length match [mils]	AD_AT length match [mils]	AD_AS1 length match [mils]	AD_AS1 max length [mils]	AD_AT max length [mils]	AD_A2+AD_AS1 max length [mils]
IO_L17N_T2_AD5N_35	FDDR_ADDR	FDDR_ADDR_3	1832	80	1912	40	100	50	60	400	2100
IO_L20P_T3_AD6P_35	FDDR_ADDR	FDDR_BA_2	1853,4	80	1912	40	100	50	60	400	2100
IO_L16N_T2_35	FDDR_ADDR	FDDR_ADDR_5	1832	80	1912	40	100	50	60	400	2100
IO_L18N_T2_AD13N_35	FDDR_ADDR	FDDR_ADDR_1	1832	80	1912	40	100	50	60	400	2100
IO_L24N_T3_AD15N_35	FDDR_ADDR	FDDR_CKE_0	1834,3	80	1912	40	100	50	60	400	2100
IO_L23P_T3_35	FDDR_ADDR	FDDR_CAS_N	1857,01	80	1912	40	100	50	60	400	2100
IO_L14N_T2_AD4N_SRCC_35	FDDR_ADDR	FDDR_ADDR_9	1832	80	1912	40	100	50	60	400	2100
IO_L24P_T3_AD15P_35	FDDR_ADDR	FDDR_CS0_N	1832	80	1912	40	100	50	60	400	2100
IO_L14P_T2_AD4P_SRCC_35	FDDR_ADDR	FDDR_ADDR_10	1832	80	1912	40	100	50	60	400	2100
IO_L15P_T2_DQS_AD12P_35	FDDR_ADDR	FDDR_ADDR_8	1832	80	1912	40	100	50	60	400	2100
IO_L15N_T2_DQS_AD12N_35	FDDR_ADDR	FDDR_ADDR_7	1832	80	1912	40	100	50	60	400	2100
IO_L12N_T1_MRCC_35	FDDR_ADDR	FDDR_RESET_N	1832	80	1912	40	100	50	60	400	2100
IO_L13P_T2_MRCC_35	FDDR_ADDR	FDDR_ADDR_12	1832	80	1912	40	100	50	60	400	2100
IO_L13N_T2_MRCC_35	FDDR_ADDR	FDDR_ADDR_11	1832	80	1912	40	100	50	60	400	2100
IO_25_35	FDDR_ADDR	FDDR_ODT_0	1832	80	1912	40	100	50	60	400	2100
IO_L23N_T3_35	FDDR_ADDR	FDDR_WE_N	1869,66	80	1912	40	100	50	60	400	2100
IO_L17P_T2_AD5P_35	FDDR_ADDR	FDDR_ADDR_4	1832	80	1912	40	100	50	60	400	2100
IO_L22N_T3_AD7N_35	FDDR_ADDR	FDDR_RAS_N	1832	80	1912	40	100	50	60	400	2100
IO_L20N_T3_AD6N_35	FDDR_ADDR	FDDR_BA_1	1832	80	1912	40	100	50	60	400	2100
IO_L18P_T2_AD13P_35	FDDR_ADDR	FDDR_ADDR_2	1853,7	80	1912	40	100	50	60	400	2100
IO_L16P_T2_35	FDDR_ADDR	FDDR_ADDR_6	1832	80	1912	40	100	50	60	400	2100
IO_L22P_T3_AD7P_35	FDDR_ADDR	FDDR_BA_0	1850,82	80	1912	40	100	50	60	400	2100
IO_L19P_T3_35	FDDR_ADDR	FDDR_ADDR_0	1836,73	80	1912	40	100	50	60	400	2100

FDDR_CK class

Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_CK class signals. The picture shows connection scheme and the nomenclature used in the table.

Bora pin name	Group name	Carrier board net name	SoM routing rules and specifications				Carrier board guidelines
			Actual length [mils]	Intra-pair match [mils]	Max length match (with respect to FDDR_ADDR group) [mils]	Nominal max length [mils]	Intra-pair match [mils]	CK_A2 pair match (with respect to FDDR_ADDR) [mils]	CK_AT intra-pair match [mils]	CK_AS1 match (with respect to FDDR_ADDR) [mils]	CK_AS1 max length [mils]	CK_AT maximum length [mils]	CK_AT pair match (with respect to FDDR_ADDR) [mils]	CK_A2+CK_AS1 max length [mils]
IO_L21P_T3_DQS_AD14P_35	FDDR_CK	FDDR_CK_P0	1900,39	5	80	1912	10	40	5	50	60	400	100	2100
IO_L21N_T3_DQS_AD14N_35	FDDR_CK	FDDR_CK_N0	1898,17	5	80	1912	10	40	5	50	60	400	100	2100

FDDR_BYTE0 class

Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE0 class signals.

Pin Name	Group name	Carrier board net name	SoM routing rules and specifications				Carrier board guidelines
			Actual length [mils]	Max length match [mils]	Max inter-pair match length on SOM [mils]	Nominal max length [mils]	Group match (mandatory) [mils]	Intra-pair match (mandatory) [mils]	Max length [mils]
IO_L2N_T0_AD8N_35	FDDR_BYTE0	FDDR_DQ_2	1222,66	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L6P_T0_35	FDDR_BYTE0	FDDR_DQ_7	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L5P_T0_AD9P_35	FDDR_BYTE0	FDDR_DQ_5	1226,42	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L4P_T0_35	FDDR_BYTE0	FDDR_DQ_3	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L2P_T0_AD8P_35	FDDR_BYTE0	FDDR_DQ_1	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L1N_T0_AD0N_35	FDDR_BYTE0	FDDR_DQ_0	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L4N_T0_35	FDDR_BYTE0	FDDR_DQ_4	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L5N_T0_AD9N_35	FDDR_BYTE0	FDDR_DQ_6	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L1P_T0_AD0P_35	FDDR_BYTE0	FDDR_DM_0	1219,68	15	-	1230	25	-	CK_A2+CK_AS1(max)
IO_L3P_T0_DQS_AD1P_35	FDDR_BYTE0	FDDR_DQS_P0	1221,04	15	5	1230	25	5	CK_A2+CK_AS1(max)
IO_L3N_T0_DQS_AD1N_35	FDDR_BYTE0	FDDR_DQS_N0	1219,42	15	5	1230	25	5	CK_A2+CK_AS1(max)

FDDR_BYTE1 class

Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE1 class signals.

Pin Name	Group name	Carrier board net name	SoM routing rules and specifications				Carrier board guidelines
			Actual length [mils]	Max length match [mils]	Max inter-pair match length on SOM [mils]	Nominal max length [mils]	Group match (mandatory) [mils]	Intra-pair match (mandatory) [mils]	Max length [mils]
IO_L10N_T1_AD11N_35	FDDR_BYTE1	FDDR_DQ_12	1345,93	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L10P_T1_AD11P_35	FDDR_BYTE1	FDDR_DQ_11	1345,93	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L11P_T1_SRCC_35	FDDR_BYTE1	FDDR_DQ_13	1353,43	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L12P_T1_MRCC_35	FDDR_BYTE1	FDDR_DQ_15	1341,3	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L11N_T1_SRCC_35	FDDR_BYTE1	FDDR_DQ_14	1340	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L8P_T1_AD10P_35	FDDR_BYTE1	FDDR_DQ_9	1340	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L7N_T1_AD2N_35	FDDR_BYTE1	FDDR_DQ_8	1340	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L8N_T1_AD10N_35	FDDR_BYTE1	FDDR_DQ_10	1340	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L7P_T1_AD2P_35	FDDR_BYTE1	FDDR_DM_1	1345,93	15	-	1355	20	-	CK_A2+CK_AS1(max)
IO_L9P_T1_DQS_AD3P_35	FDDR_BYTE1	FDDR_DQS_P1	1354,26	15	5	1355	20	5	CK_A2+CK_AS1(max)
IO_L9N_T1_DQS_AD3N_35	FDDR_BYTE1	FDDR_DQS_N1	1350,66	15	5	1355	20	5	CK_A2+CK_AS1(max)

VREF

Recommendations:

• use a "T" connection as shown by following picture
• use 20+ mils trace
• place bypass capacitors as close as possible to power balls.

Other signals

The following table lists other signals that do not follow specific routing rules.

Bora pin name	Trace length [mils]
IO_0_35	1171,03
IO_L19N_T3_VREF_35	2053,07
IO_L6N_T0_VREF_35	2295,83

Related Xilinx documentation

• Xilinx Memory Interface Solutions UG586
• Xilinx Memory Interface Solutions Data Sheet

FPGA Bank 13 (Zynq 7020 only)

N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway, either to ground or to an external I/O voltage as described in I/O banks table.

The following table reports the available pins connected to bank 13:

Pin Name	Conn. Pin	Notes
IO_L11N_T1_SRCC_13	J3.136
IO_L11P_T1_SRCC_13	J3.134
IO_L12N_T1_MRCC_13	J3.137
IO_L12P_T1_MRCC_13	J3.135
IO_L13N_T2_MRCC_13	J3.130
IO_L13P_T2_MRCC_13	J3.128
IO_L14N_T2_SRCC_13	J3.131
IO_L14P_T2_SRCC_13	J3.129
IO_L15N_T2_DQS_13	J3.124
IO_L15P_T2_DQS_13	J3.122
IO_L16N_T2_13	J3.125
IO_L16P_T2_13	J3.123
IO_L17N_T2_13	J3.118
IO_L17P_T2_13	J3.116
IO_L18N_T2_13	J3.119
IO_L18P_T2_13	J3.117
IO_L19N_T3_VREF_13	J3.113
IO_L19P_T3_13	J3.111
IO_L20N_T3_13	J3.112
IO_L20P_T3_13	J3.110
IO_L21N_T3_DQS_13	J3.107
IO_L21P_T3_DQS_13	J3.105
IO_L22N_T3_13	J3.106
IO_L22P_T3_13	J3.104
IO_L6N_T0_VREF_13	J3.100

Regarding power voltage, Bank 13 is configurable and must be powered by carrier board. For routing details, please refer to PL Bank 13 routing.

Routing information

Routing implemented on Bora SoM allows the use of bank 13's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.

Pairs are highlighted with different colors. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohm.

Bora pin name	Individual net length [mils]	Intra-pair match [mils]	Inter-pair match [mils]	Group Name
IO_L15N_T2_DQS_13	1582,37	25	200	BANK13 Diff group 1
IO_L15P_T2_DQS_13	1602,37	25	200	BANK13 Diff group 1
IO_L16N_T2_13	1589,32	25	200	BANK13 Diff group 1
IO_L16P_T2_13	1602,33	25	200	BANK13 Diff group 1
IO_L17N_T2_13	1710,41	25	200	BANK13 Diff group 1
IO_L17P_T2_13	1722,73	25	200	BANK13 Diff group 1
IO_L18N_T2_13	1720,53	25	200	BANK13 Diff group 1
IO_L18P_T2_13	1712,11	25	200	BANK13 Diff group 1
IO_L19N_T3_VREF_13	1585,55	25	200	BANK13 Diff group 1
IO_L19P_T3_13	1602,96	25	200	BANK13 Diff group 1
IO_L20N_T3_13	1623,95	25	200	BANK13 Diff group 1
IO_L20P_T3_13	1626,27	25	200	BANK13 Diff group 1
IO_L21N_T3_DQS_13	1661,55	25	200	BANK13 Diff group 1
IO_L21P_T3_DQS_13	1668,95	25	200	BANK13 Diff group 1
IO_L22N_T3_13	1592,18	25	200	BANK13 Diff group 1
IO_L22P_T3_13	1577,63	25	200	BANK13 Diff group 1
IO_L11N_T1_SRCC_13	1702,04	10	50	BANK13 xRCC group
IO_L11P_T1_SRCC_13	1705,07	10	50	BANK13 xRCC group
IO_L12N_T1_MRCC_13	1704,42	10	50	BANK13 xRCC group
IO_L12P_T1_MRCC_13	1703,11	10	50	BANK13 xRCC group
IO_L13N_T2_MRCC_13	1731,33	10	50	BANK13 xRCC group
IO_L13P_T2_MRCC_13	1732,15	10	50	BANK13 xRCC group
IO_L14N_T2_SRCC_13	1710,12	10	50	BANK13 xRCC group
IO_L14P_T2_SRCC_13	1716,36	10	50	BANK13 xRCC group

Other signals

The following table lists other signals that do not follow specific routing rules.

Bora pin name	Trace length [mils]
IO_L6N_T0_VREF_13	1098,15