BORA Lite SOM/BORA Lite Hardware

BORA Lite SOM HW Manual
BORA Lite TOP view BORA Lite Block diagram Processor and memory subsystem Hardware versioning and tracking BORA Lite SOM Part number composition BORA Lite SOM RFQ Request For Quotation	Customers are strongly recommended to register their kits. Registration grants access to reserved material such as source code and additional documentation. To register the kit, please send an email to helpdesk@dave.eu, providing the kit P/N and S/N. BORA Lite Hw Manual

Connectors and Pinout		Power and Reset		Peripherals		Electrical, Thermal and Mechanical Features
Connectors and Pinout Table SODIMM ODD pins declaration SODIMM EVEN pins declaration		Power Supply Unit (PSU) and recommended power-up sequence Reset scheme and control signals PL initialization signals System boot JTAG		Processing System (PS) Programmable logic (FPGA) Ethernet SDIO SPI NAND I2C UART USB EEPROM Real Time Clock Watchdog		Operational characteristics Thermal management and heat dissipation Mechanical specifications