BELK-TN-013: Managing ethernet and USB physical transceivers reset

Info Box Applies to Bora Applies to BORA Xpress Applies to BORA Lite Applies to BORA Technical Notes Applies to BORA Xpress Technical Notes Applies to BORA Lite Technical Notes

This technical note was validated against specific versions of hardware and software. What is described here may not work with other versions.

Contents

HistoryEdit

Version	Date	BELK/BXELK version	Notes
1.0.0	Apri 2022	4.1.5	First release

IntroductionEdit

This technical note provides some information for managing the rest of Ethernet and USB physical transceivers used in BORA, BORA Xpress and BORA Lite DAVE Embedded Systems' SOMs.

ReferenceEdit

The BORA and BORA Xpress ethernet and USB PHY reset signals are actually managed by the two MIO pins dedicated to this functionality. The MIO pins are documented in the Power and Reset wiki page for PS MIO51 501 and PS MIO50 501 pins.

Hardware reset using MIO pinsEdit

The default configuration for the two PHY is managed - by default - in the BORA and BORA Xpress SOMS using the two dedicated MIO pins.

Those MIO pins are connected to the PHY reset signals and the reset pulse is generated at software levels.

U-Boot PHY resetEdit

In the BELK BSP, the following U-Boot routine contains the reset pulse generation:

int board_init(void)

In this specific case, the reset pulse is generated directly by writing in the MIO registers as per the following source code:

	/*
	 * temporary hack to take USB0 out of reset
	 */
	temp = readl(0xE000A244);
	writel(temp | USB0_rst , 0xE000A244);
	temp = readl(0xE000A248);
	writel(temp | USB0_rst , 0xE000A248);
	temp = readl(0xE000A044);
	writel(temp & ~USB0_rst , 0xE000A044);
	udelay(10000); // pause for 10ms
	temp = readl(0xE000A044);
	writel(temp | USB0_rst , 0xE000A044);

	/*
	 * temporary hack to take ETH PHY out of reset
	 */
	temp = readl(0xE000A244);
	writel((temp | ETH0_rst) , 0xE000A244);
	temp = readl(0xE000A248);
	writel((temp | ETH0_rst), 0xE000A248);
	writel((temp & ~ETH0_rst), 0xE000A044);
	mdelay(500); /* 500ms */
	temp = readl(0xE000A044);
	writel((temp | ETH0_rst), 0xE000A044);

kernel PHY resetEdit

The Linux kernel is assumed to find the two physical transceivers already reset. So, the hardware reset is not implemented at driver nor userspace levels.

For issuing a reset pulse to the PHYs, a dedicated kernel hacking is to be realized; this taking into account:

• the status of software protocols stack
• the component driver
  • the ethernet PHY is a Micrel KSZ9031 and so its related drivers/net/phy/micrel.c kernel driver
  • the USB PHY is a
• the PHY re-initialization (see for example [this] article

i.e. a proper BSP modifications have to be evaluated.