BELK-TN-013: Managing ethernet and USB physical transceivers reset

Info Box Applies to Bora Applies to BORA Xpress Applies to BORA Lite Applies to BORA Technical Notes Applies to BORA Xpress Technical Notes Applies to BORA Lite Technical Notes

This technical note was validated against specific versions of hardware and software. What is described here may not work with other versions.

History

Version	Date	BELK/BXELK version	Notes
1.0.0	Apri 2022	4.1.5	First release

Introduction

This technical note provides some information for managing the reset of Ethernet and USB physical transceivers used in BORA, BORA Xpress and BORA Lite DAVE Embedded Systems' SOMs.

Reference

The BORA and BORA Xpress ethernet and USB PHY reset signals are actually managed by the two MIO pins dedicated to this functionality. The MIO pins are documented in the Power and Reset wiki page for PS MIO51 501 and PS MIO50 501 pins.

Hardware reset using MIO pins

The default configuration for the two PHY is managed - by default - in the BORA and BORA Xpress SOMS using the two dedicated MIO pins.

Those MIO pins are connected to the PHY reset signals and the reset pulse is generated at software levels.

U-Boot PHY reset

In the BELK BSP, the following U-Boot routine contains the reset pulse generation:

int board_init(void)

In this specific case, the reset pulse is generated directly by writing in the MIO registers as per the following source code:

	/*
	 * temporary hack to take USB0 out of reset
	 */
	temp = readl(0xE000A244);
	writel(temp | USB0_rst , 0xE000A244);
	temp = readl(0xE000A248);
	writel(temp | USB0_rst , 0xE000A248);
	temp = readl(0xE000A044);
	writel(temp & ~USB0_rst , 0xE000A044);
	udelay(10000); // pause for 10ms
	temp = readl(0xE000A044);
	writel(temp | USB0_rst , 0xE000A044);

	/*
	 * temporary hack to take ETH PHY out of reset
	 */
	temp = readl(0xE000A244);
	writel((temp | ETH0_rst) , 0xE000A244);
	temp = readl(0xE000A248);
	writel((temp | ETH0_rst), 0xE000A248);
	writel((temp & ~ETH0_rst), 0xE000A044);
	mdelay(500); /* 500ms */
	temp = readl(0xE000A044);
	writel((temp | ETH0_rst), 0xE000A044);

kernel PHY reset

The Linux kernel is assumed to find the two physical transceivers already reset. So, the hardware reset is not implemented at driver nor userspace levels.

ethernet

The ethernet PHY kernel driver, i.e. drivers/net/ethernet/cadence/macb.c supports a device tree entry for generating the hardware reset pulse.

It is enough to add the following entries in order to let the kernel to reset the PHY too:

&gem0 {
   status = "okay";
   phy-mode = "rgmii-id";
   phy-handle = <&phy0>;
   phy-reset-gpio = <&gpio0 51 1>;
   phy-reset-duration = <100>;
   phy-reset-active-low;
...
...

USB

For issuing a reset pulse to the USB PHY, a dedicated kernel hacking is to be realized; the USB PHY driver is the ULPI drivers/usb/phy/phy-ulpi.c kernel driver and then the proper BSP modifications have to be evaluated.

An example of a USB driver with the hardware reset can be found on drivers/usb/phy/phy-generic.c and the related reset management can be used as a reference for implementing the hacking in the ULPI driver.

Software reset

The ethernet PHY - in general - supports a software reset too.