Difference between revisions of "AXEL Lite SOM/AXEL Lite Hardware/Pinout Table"

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−
<section begin=History/>
+
<section begin="History" />
 
{| style="border-collapse:collapse; "
 
{| style="border-collapse:collapse; "
−
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
+
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
|-  
 
|-  
−
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version
+
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
−
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
+
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
−
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
 
 
|-
 
|-
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|1.0.0
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|13761|2020/12/18}}
−
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Sep 2020
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |New documentation layout
−
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout
 
 
|-
 
|-
 +
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|15218|2021/11/17}}
 +
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |More details about BOOT_MODE_SEL signal
 +
|-
 +
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/11/26
 +
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Voltage domains legend added. Fixed the "Type" field of ETH0_LED1 and ETH0_LED2.
 +
|}
 +
<section end="History" />
 +
<section begin="Body" />
 +
==Connectors and Pinout Table==
  
 +
=== Connectors description ===
 +
In the following table are described all available connectors integrated on [[AXEL Lite SOM]]:
 +
{| class="wikitable"
 +
|-
 +
!Connector name
 +
!Connector Type
 +
!Notes
 +
!Carrier board counterpart
 +
|-
 +
|J1
 +
|SODIMM DDR3 edge connector 204 pin
 +
|
 +
|TE Connectivity 2-2013289-1
 
|}
 
|}
−
<section end=History/>
+
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AXEL Lite pinout specifications. See the images below for reference:
−
<section begin=Body/>
 
−
==Pinout Table==
 
  
−
===Introduction===
+
[[File:AXEL_Lite-top-pin1-203.png|500px|thumb|AXEL Lite TOP view|none]]
 +
[[File:AXEL_Lite-bottom-pin2-204.png|500px|thumb|AXEL Lite BOTTOM view|none]]
  
−
This chapter contains the pinout description of the AXEL Lite module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM AXEL Lite connector.
+
===Pinout table naming conventions ===
 +
 
 +
This chapter contains the pinout description of the [[AXEL Lite SOM]] module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM connector.
  
 
Each row in the pinout tables contains the following information:
 
Each row in the pinout tables contains the following information:
  
−
{|class="wikitable" style="width:50%;"
+
{| class="wikitable"
 
|-
 
|-
 
|'''Pin'''
 
|'''Pin'''
Line 32: Line 53:
 
|-
 
|-
 
|'''Internal<br>connections'''  
 
|'''Internal<br>connections'''  
−
| Connections to the Axel Ultra components
+
| Connections to the components
 
* CPU.<x> : pin connected to CPU pad named <x>
 
* CPU.<x> : pin connected to CPU pad named <x>
−
* CAN.<x> : pin connected to the CAN transceiver
+
* CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232)
−
* PMIC.<x> : pin connected to the Power Manager IC
+
* PMIC.<x> : pin connected to the Power Manager IC (NXP MMPF0100)
−
* LAN.<x> : pin connected to the LAN PHY
+
* LAN.<x> : pin connected to the LAN PHY (Microchip KSZ9031)
 
* NOR.<x>: pin connected to the flash NOR
 
* NOR.<x>: pin connected to the flash NOR
 
* SV.<x>: pin connected to voltage supervisor
 
* SV.<x>: pin connected to voltage supervisor
Line 44: Line 65:
 
| Component ball/pin number connected to signal
 
| Component ball/pin number connected to signal
 
|-
 
|-
−
|'''Voltage''' || I/O voltage levels
+
|'''Voltage domain''' || The voltage domain the pin belongs to
 
|-
 
|-
 
|'''Type'''  
 
|'''Type'''  
Line 73: Line 94:
 
|}
 
|}
  
−
===Pinout Table ODD pins declaration ===
+
===Voltage domains ===
 +
 
 +
{| class="wikitable"
 +
! latexfontsize="scriptsize" | Voltage domain
 +
! latexfontsize="scriptsize" | Nominal voltage [V]
 +
! latexfontsize="scriptsize" | Notes
 +
|-
 +
|3.3VIN
 +
|3.3
 +
|See [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Electrical_Thermal_and_Mechanical_Features/Operational_characteristics#Recommended_ratings|Operational_characteristics]] of the SoM wiki page
 +
|-
 +
|VCC_ENET_1V8
 +
|1.8
 +
|Voltage generated by the internal PSU. See [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
 +
|-
 +
|AXEL_IO_3V3
 +
|3.3
 +
|Voltage generated by the internal PSU. See [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
 +
|-
 +
|GEN_2V5
 +
|2.5
 +
|Voltage generated by the internal PSU. See [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
 +
|-
 +
|}
 +
 
 +
==SODIMM ODD pins declaration ==
  
 
{| class="wikitable"  
 
{| class="wikitable"  
−
! latexfontsize="scriptsize"| Pin  
+
! latexfontsize="scriptsize" | Pin  
−
! latexfontsize="scriptsize"| Pin Name
+
! latexfontsize="scriptsize" | Pin Name
−
! latexfontsize="scriptsize"| Internal Connections  
+
! latexfontsize="scriptsize" | Internal Connections  
−
! latexfontsize="scriptsize"| Ball/pin #  
+
! latexfontsize="scriptsize" | Ball/pin #  
−
! latexfontsize="scriptsize"| Voltage|domain
+
! latexfontsize="scriptsize" |Voltage
−
! latexfontsize="scriptsize"| Type  
+
domain
−
! latexfontsize="scriptsize"| Notes
+
! latexfontsize="scriptsize" | Type  
−
! colspan="2" latexfontsize="scriptsize"| Alternative Functions
+
! latexfontsize="scriptsize" | Notes
 +
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
 
|-
 
|-
 
|J2.1
 
|J2.1
Line 150: Line 197:
 
|17
 
|17
 
|VCC_ENET_1V8
 
|VCC_ENET_1V8
−
|D
+
|O
−
|This signal is @ 1.8V and should be|level translated if used @ 3V3
+
| This signal is @ 1.8V and should be |Internal 10k pull-up to 1.8V
 +
This signal requires voltage level shifters if used at 3.3V
 
|
 
|
 
|
 
|
Line 160: Line 208:
 
|15
 
|15
 
|VCC_ENET_1V8
 
|VCC_ENET_1V8
−
|D
+
|O
−
|This signal is @ 1.8V and should be|level translated if used @ 3V3
+
| This signal is @ 1.8V and should be |Internal 10k pull-up to 1.8V
 +
This signal requires voltage level shifters if used at 3.3V
 
|
 
|
 
|
 
|
Line 265: Line 314:
 
|
 
|
 
|-
 
|-
−
|rowspan="3"| J2.37
+
| rowspan="3" | J2.37
−
|rowspan="3"| SD3_RST
+
| rowspan="3" | SD3_RST
−
|rowspan="3"| CPU.SD3_RST
+
| rowspan="3" | CPU.SD3_RST
−
|rowspan="3"| D15
+
| rowspan="3" | D15
−
|rowspan="3"| AXEL_IO_3V3
+
| rowspan="3" | AXEL_IO_3V3
−
|rowspan="3"| IO
+
| rowspan="3" | IO
−
|rowspan="3"|  
+
| rowspan="3" |  
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_RESET
 
|SD3_RESET
Line 281: Line 330:
 
|GPIO7_IO08
 
|GPIO7_IO08
 
|-
 
|-
−
|rowspan="4"|J2.39
+
| rowspan="4" |J2.39
−
|rowspan="4"|SD3_DATA0
+
| rowspan="4" |SD3_DATA0
−
|rowspan="4"|CPU.SD3_DATA0
+
| rowspan="4" |CPU.SD3_DATA0
−
|rowspan="4"|E14
+
| rowspan="4" |E14
−
|rowspan="4"|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|rowspan="4"|IO
+
| rowspan="4" |IO
−
|rowspan=4"|
+
| rowspan="4&quot;" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_DATA0
 
|SD3_DATA0
Line 300: Line 349:
 
|GPIO7_IO04
 
|GPIO7_IO04
 
|-
 
|-
−
|rowspan="4"|J2.41
+
| rowspan="4" |J2.41
−
|rowspan="4"|SD3_DATA1
+
| rowspan="4" |SD3_DATA1
−
|rowspan="4"|CPU.SD3_DATA1
+
| rowspan="4" |CPU.SD3_DATA1
−
|rowspan="4"|F14
+
| rowspan="4" |F14
−
|rowspan="4"|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|rowspan="4"|IO
+
| rowspan="4" |IO
−
|rowspan="4"|
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_DATA1
 
|SD3_DATA1
Line 319: Line 368:
 
|GPIO7_IO05
 
|GPIO7_IO05
 
|-
 
|-
−
|rowspan="2"|J2.43
+
| rowspan="2" |J2.43
−
|rowspan="2"|SD3_DATA2
+
| rowspan="2" |SD3_DATA2
−
|rowspan="2"|CPU.SD3_DATA2
+
| rowspan="2" |CPU.SD3_DATA2
−
|rowspan="2"|A15
+
| rowspan="2" |A15
−
|rowspan="2"|AXEL_IO_3V3
+
| rowspan="2" |AXEL_IO_3V3
−
|rowspan="2"|IO
+
| rowspan="2" |IO
−
|rowspan="2"|
+
| rowspan="2" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_DATA2
 
|SD3_DATA2
Line 332: Line 381:
 
|GPIO7_IO06
 
|GPIO7_IO06
 
|-
 
|-
−
|rowspan="3"|J2.45
+
| rowspan="3" |J2.45
−
|rowspan="3"|SD3_DATA3
+
| rowspan="3" |SD3_DATA3
−
|rowspan="3"|CPU.SD3_DATA3
+
| rowspan="3" |CPU.SD3_DATA3
−
|rowspan="3"|B15
+
| rowspan="3" |B15
−
|rowspan="3"|AXEL_IO_3V3
+
| rowspan="3" |AXEL_IO_3V3
−
|rowspan="3"|IO
+
| rowspan="3" |IO
−
|rowspan="3"|
+
| rowspan="3" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_DATA3
 
|SD3_DATA3
Line 348: Line 397:
 
|GPIO7_IO07
 
|GPIO7_IO07
 
|-
 
|-
−
|rowspan="3"|J2.47
+
| rowspan="3" |J2.47
−
|rowspan="3"|SD3_DATA4
+
| rowspan="3" |SD3_DATA4
−
|rowspan="3"|CPU.SD3_DATA4
+
| rowspan="3" |CPU.SD3_DATA4
−
|rowspan="3"|D13
+
| rowspan="3" |D13
−
|rowspan="3"|AXEL_IO_3V3
+
| rowspan="3" |AXEL_IO_3V3
−
|rowspan="3"|IO
+
| rowspan="3" |IO
−
|rowspan="3"|
+
| rowspan="3" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_DATA4
 
|SD3_DATA4
Line 364: Line 413:
 
|GPIO7_IO01
 
|GPIO7_IO01
 
|-
 
|-
−
|rowspan="3"|J2.49
+
| rowspan="3" |J2.49
−
|rowspan="3"|SD3_DATA5
+
| rowspan="3" |SD3_DATA5
−
|rowspan="3"|CPU.SD3_DATA5
+
| rowspan="3" |CPU.SD3_DATA5
−
|rowspan="3"|C13
+
| rowspan="3" |C13
−
|rowspan="3"|AXEL_IO_3V3
+
| rowspan="3" |AXEL_IO_3V3
−
|rowspan="3"|IO
+
| rowspan="3" |IO
−
|rowspan="3"|
+
| rowspan="3" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_DATA5
 
|SD3_DATA5
Line 380: Line 429:
 
|GPIO7_IO00
 
|GPIO7_IO00
 
|-
 
|-
−
|rowspan="3"|J2.51
+
| rowspan="3" |J2.51
−
|rowspan="3"|SD3_DATA6
+
| rowspan="3" |SD3_DATA6
−
|rowspan="3"|CPU.SD3_DATA6
+
| rowspan="3" |CPU.SD3_DATA6
−
|rowspan="3"|E13
+
| rowspan="3" |E13
−
|rowspan="3"|AXEL_IO_3V3
+
| rowspan="3" |AXEL_IO_3V3
−
|rowspan="3"|IO
+
| rowspan="3" |IO
−
|rowspan="3"|
+
| rowspan="3" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_DATA6
 
|SD3_DATA6
Line 396: Line 445:
 
|GPIO6_IO18
 
|GPIO6_IO18
 
|-
 
|-
−
|rowspan="3"|J2.53
+
| rowspan="3" |J2.53
−
|rowspan="3"|SD3_DATA7
+
| rowspan="3" |SD3_DATA7
−
|rowspan="3"|CPU.SD3_DATA7
+
| rowspan="3" |CPU.SD3_DATA7
−
|rowspan="3"|F13
+
| rowspan="3" |F13
−
|rowspan="3"|AXEL_IO_3V3
+
| rowspan="3" |AXEL_IO_3V3
−
|rowspan="3"|IO
+
| rowspan="3" |IO
−
|rowspan="3"|
+
| rowspan="3" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_DATA7
 
|SD3_DATA7
Line 412: Line 461:
 
|GPIO6_IO17
 
|GPIO6_IO17
 
|-
 
|-
−
|rowspan="4"|J2.55
+
| rowspan="4" |J2.55
−
|rowspan="4"|SD3_CMD
+
| rowspan="4" |SD3_CMD
−
|rowspan="4"|CPU.SD3_CMD
+
| rowspan="4" |CPU.SD3_CMD
−
|rowspan="4"|B13
+
| rowspan="4" |B13
−
|rowspan="4"|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|rowspan="4"|IO
+
| rowspan="4" |IO
−
|rowspan="4"|
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_CMD
 
|SD3_CMD
Line 441: Line 490:
 
|
 
|
 
|-
 
|-
−
|rowspan="4"|J2.59
+
| rowspan="4" |J2.59
−
|rowspan="4"|SD3_CLK
+
| rowspan="4" |SD3_CLK
−
|rowspan="4"|CPU.SD3_CLK
+
| rowspan="4" |CPU.SD3_CLK
−
|rowspan="4"|D14
+
| rowspan="4" |D14
−
|rowspan="4"|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|rowspan="4"|IO
+
| rowspan="4" |IO
−
|rowspan="4"|
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD3_CLK
 
|SD3_CLK
Line 460: Line 509:
 
|GPIO7_IO03
 
|GPIO7_IO03
 
|-
 
|-
−
|rowspan="6"|J2.61
+
| rowspan="6" |J2.61
−
|rowspan="6"|SD2_DATA0
+
| rowspan="6" |SD2_DATA0
−
|rowspan="6"|CPU.SD2_DATA0
+
| rowspan="6" |CPU.SD2_DATA0
−
|rowspan="6"|A22
+
| rowspan="6" |A22
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD2_DATA0
 
|SD2_DATA0
Line 485: Line 534:
 
|DCIC2_OUT
 
|DCIC2_OUT
 
|-
 
|-
−
|rowspan="6"|J2.63
+
| rowspan="6" |J2.63
−
|rowspan="6"|SD2_DATA1
+
| rowspan="6" |SD2_DATA1
−
|rowspan="6"|CPU.SD2_DATA1
+
| rowspan="6" |CPU.SD2_DATA1
−
|rowspan="6"|E20
+
| rowspan="6" |E20
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD2_DATA1
 
|SD2_DATA1
Line 510: Line 559:
 
|GPIO1_IO14
 
|GPIO1_IO14
 
|-
 
|-
−
|rowspan="6"|J2.65
+
| rowspan="6" |J2.65
−
|rowspan="6"|SD2_DATA2
+
| rowspan="6" |SD2_DATA2
−
|rowspan="6"|CPU.SD2_DATA2
+
| rowspan="6" |CPU.SD2_DATA2
−
|rowspan="6"|A23
+
| rowspan="6" |A23
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD2_DATA2
 
|SD2_DATA2
Line 535: Line 584:
 
|GPIO1_IO13
 
|GPIO1_IO13
 
|-
 
|-
−
|rowspan="5"|J2.67
+
| rowspan="5" |J2.67
−
|rowspan="5"|SD2_DATA3
+
| rowspan="5" |SD2_DATA3
−
|rowspan="5"|CPU.SD2_DATA3
+
| rowspan="5" |CPU.SD2_DATA3
−
|rowspan="5"|B22
+
| rowspan="5" |B22
−
|rowspan="5"|AXEL_IO_3V3
+
| rowspan="5" |AXEL_IO_3V3
−
|rowspan="5"|IO
+
| rowspan="5" |IO
−
|rowspan="5"|
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD2_DATA3
 
|SD2_DATA3
Line 557: Line 606:
 
|GPIO1_IO12
 
|GPIO1_IO12
 
|-
 
|-
−
|rowspan="5"|J2.69
+
| rowspan="5" |J2.69
−
|rowspan="5"|SD2_CMD
+
| rowspan="5" |SD2_CMD
−
|rowspan="5"|CPU.SD2_CMD
+
| rowspan="5" |CPU.SD2_CMD
−
|rowspan="5"|F19
+
| rowspan="5" |F19
−
|rowspan="5"|AXEL_IO_3V3
+
| rowspan="5" |AXEL_IO_3V3
−
|rowspan="5"|IO
+
| rowspan="5" |IO
−
|rowspan="5"|
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD2_CMD
 
|SD2_CMD
Line 579: Line 628:
 
|GPIO1_IO11
 
|GPIO1_IO11
 
|-
 
|-
−
|rowspan="5"|J2.71
+
| rowspan="5" |J2.71
−
|rowspan="5"|SD2_CLK
+
| rowspan="5" |SD2_CLK
−
|rowspan="5"|CPU.SD2_CLK
+
| rowspan="5" |CPU.SD2_CLK
−
|rowspan="5"|C21
+
| rowspan="5" |C21
−
|rowspan="5"|AXEL_IO_3V3
+
| rowspan="5" |AXEL_IO_3V3
−
|rowspan="5"|IO
+
| rowspan="5" |IO
−
|rowspan="5"|
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD2_CLK
 
|SD2_CLK
Line 611: Line 660:
 
|
 
|
 
|-
 
|-
−
|rowspan="4"|J2.75
+
| rowspan="4" |J2.75
−
|rowspan="4"|SD1_DAT0
+
| rowspan="4" |SD1_DAT0
−
|rowspan="4"|CPU.SD1_DAT0
+
| rowspan="4" |CPU.SD1_DAT0
−
|rowspan="4"|A21
+
| rowspan="4" |A21
−
|rowspan="4"|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|rowspan="4"|IO
+
| rowspan="4" |IO
−
|rowspan="4"|
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD1_DATA0
 
|SD1_DATA0
Line 630: Line 679:
 
|GPIO1_IO16
 
|GPIO1_IO16
 
|-
 
|-
−
|rowspan="5"|J2.77
+
| rowspan="5" |J2.77
−
|rowspan="5"|SD1_DAT1
+
| rowspan="5" |SD1_DAT1
−
|rowspan="5"|CPU.SD1_DAT1
+
| rowspan="5" |CPU.SD1_DAT1
−
|rowspan="5"|C20
+
| rowspan="5" |C20
−
|rowspan="5"|AXEL_IO_3V3
+
| rowspan="5" |AXEL_IO_3V3
−
|rowspan="5"|IO
+
| rowspan="5" |IO
−
|rowspan="5"|
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD1_DATA1
 
|SD1_DATA1
Line 652: Line 701:
 
|GPIO1_IO17
 
|GPIO1_IO17
 
|-
 
|-
−
|rowspan="7"|J2.79
+
| rowspan="7" |J2.79
−
|rowspan="7"|SD1_DAT2
+
| rowspan="7" |SD1_DAT2
−
|rowspan="7"|CPU.SD1_DAT2
+
| rowspan="7" |CPU.SD1_DAT2
−
|rowspan="7"|E19
+
| rowspan="7" |E19
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD1_DATA2
 
|SD1_DATA2
Line 680: Line 729:
 
|WDOG1_RESET_B_DEB
 
|WDOG1_RESET_B_DEB
 
|-
 
|-
−
|rowspan="7"|J2.81
+
| rowspan="7" |J2.81
−
|rowspan="7"|SD1_DAT3
+
| rowspan="7" |SD1_DAT3
−
|rowspan="7"|CPU.SD1_DAT3
+
| rowspan="7" |CPU.SD1_DAT3
−
|rowspan="7"|F18
+
| rowspan="7" |F18
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD1_DATA3
 
|SD1_DATA3
Line 708: Line 757:
 
|WDOG2_RESET_B_DEB
 
|WDOG2_RESET_B_DEB
 
|-
 
|-
−
|rowspan="5"|J2.83
+
| rowspan="5" |J2.83
−
|rowspan="5"|SD1_CMD
+
| rowspan="5" |SD1_CMD
−
|rowspan="5"|CPU.SD1_CMD
+
| rowspan="5" |CPU.SD1_CMD
−
|rowspan="5"|B21
+
| rowspan="5" |B21
−
|rowspan="5"|AXEL_IO_3V3
+
| rowspan="5" |AXEL_IO_3V3
−
|rowspan="5"|IO
+
| rowspan="5" |IO
−
|rowspan="5"|
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD1_CMD
 
|SD1_CMD
Line 730: Line 779:
 
|GPIO1_IO18
 
|GPIO1_IO18
 
|-
 
|-
−
|rowspan="4"|J2.85
+
| rowspan="4" |J2.85
−
|rowspan="4"|SD1_CLK
+
| rowspan="4" |SD1_CLK
−
|rowspan="4"|CPU.SD1_CLK
+
| rowspan="4" |CPU.SD1_CLK
−
|rowspan="4"|D20
+
| rowspan="4" |D20
−
|rowspan="4"|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|rowspan="4"|IO
+
| rowspan="4" |IO
−
|rowspan="4"|
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|SD1_CLK
 
|SD1_CLK
Line 759: Line 808:
 
|
 
|
 
|-
 
|-
−
|rowspan="7"|J2.89
+
| rowspan="7" |J2.89
−
|rowspan="7"|KEY_COL0/|ECSPI1_SCLK
+
| rowspan="7" |<nowiki>KEY_COL0/|ECSPI1_SCLK</nowiki>
−
|rowspan="7"|CPU.KEY_COL0
+
| rowspan="7" |CPU.KEY_COL0
−
|rowspan="7"|W5
+
| rowspan="7" |W5
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_SCLK
 
|ECSPI1_SCLK
Line 787: Line 836:
 
|DCIC1_OUT
 
|DCIC1_OUT
 
|-
 
|-
−
|rowspan="7"|J2.91
+
| rowspan="7" |J2.91
−
|rowspan="7"|KEY_ROW0/|ECSPI1_MOSI
+
| rowspan="7" |<nowiki>KEY_ROW0/|ECSPI1_MOSI</nowiki>
−
|rowspan="7"|CPU.KEY_ROW0
+
| rowspan="7" |CPU.KEY_ROW0
−
|rowspan="7"|V6
+
| rowspan="7" |V6
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_MOSI
 
|ECSPI1_MOSI
Line 815: Line 864:
 
|DCIC2_OUT
 
|DCIC2_OUT
 
|-
 
|-
−
|rowspan="7"|J2.93
+
| rowspan="7" |J2.93
−
|rowspan="7"|KEY_COL1/|ECSPI1_MISO
+
| rowspan="7" |<nowiki>KEY_COL1/|ECSPI1_MISO</nowiki>
−
|rowspan="7"|CPU.KEY_COL1
+
| rowspan="7" |CPU.KEY_COL1
−
|rowspan="7"|U7
+
| rowspan="7" |U7
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_MISO
 
|ECSPI1_MISO
Line 843: Line 892:
 
|SD1_VSELECT
 
|SD1_VSELECT
 
|-
 
|-
−
|rowspan="7"|J2.95
+
| rowspan="7" |J2.95
−
|rowspan="7"|KEY_ROW1/|ECSPI1_SS0
+
| rowspan="7" |<nowiki>KEY_ROW1/|ECSPI1_SS0</nowiki>
−
|rowspan="7"|CPU.KEY_ROW1
+
| rowspan="7" |CPU.KEY_ROW1
−
|rowspan="7"|U6
+
| rowspan="7" |U6
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_SS0
 
|ECSPI1_SS0
Line 871: Line 920:
 
|SD2_VSELECT
 
|SD2_VSELECT
 
|-
 
|-
−
|rowspan="7"|J2.97
+
| rowspan="7" |J2.97
−
|rowspan="7"|KEY_COL2/|ECSPI1_SS1
+
| rowspan="7" |<nowiki>KEY_COL2/|ECSPI1_SS1</nowiki>
−
|rowspan="7"|CPU.KEY_COL2
+
| rowspan="7" |CPU.KEY_COL2
−
|rowspan="7"|W6
+
| rowspan="7" |W6
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_SS1
 
|ECSPI1_SS1
Line 899: Line 948:
 
|USB_H1_PWR_CTL_WAKE
 
|USB_H1_PWR_CTL_WAKE
 
|-
 
|-
−
|rowspan="7"|J2.99
+
| rowspan="7" |J2.99
−
|rowspan="7"|KEY_ROW2
+
| rowspan="7" |KEY_ROW2
−
|rowspan="7"|CPU.KEY_ROW2
+
| rowspan="7" |CPU.KEY_ROW2
−
|rowspan="7"|W4
+
| rowspan="7" |W4
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_SS2
 
|ECSPI1_SS2
Line 927: Line 976:
 
|HDMI_TX_CEC_LINE
 
|HDMI_TX_CEC_LINE
 
|-
 
|-
−
|rowspan="7"|J2.101
+
| rowspan="7" |J2.101
−
|rowspan="7"|KEY_COL3/|I2C2_SCL
+
| rowspan="7" |<nowiki>KEY_COL3/|I2C2_SCL</nowiki>
−
|rowspan="7"|CPU.KEY_COL3
+
| rowspan="7" |CPU.KEY_COL3
−
|rowspan="7"|U5
+
| rowspan="7" |U5
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|Internally connected to PMIC I2C interface
+
| rowspan="7" |Internally connected to PMIC I2C interface
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_SS3
 
|ECSPI1_SS3
Line 955: Line 1,004:
 
|SPDIF_IN
 
|SPDIF_IN
 
|-
 
|-
−
|rowspan="6"|J2.103
+
| rowspan="6" |J2.103
−
|rowspan="6"|KEY_ROW3/|I2C2_SDA
+
| rowspan="6" |<nowiki>KEY_ROW3/|I2C2_SDA</nowiki>
−
|rowspan="6"|CPU.KEY_ROW3
+
| rowspan="6" |CPU.KEY_ROW3
−
|rowspan="6"|T7
+
| rowspan="6" |T7
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|Internally connected to PMIC I2C interface
+
| rowspan="6" |Internally connected to PMIC I2C interface
 
|Pin ALT-1
 
|Pin ALT-1
 
|ASRC_EXT_CLK
 
|ASRC_EXT_CLK
Line 980: Line 1,029:
 
|SD1_VSELECT
 
|SD1_VSELECT
 
|-
 
|-
−
|rowspan="6"|J2.105
+
| rowspan="6" |J2.105
−
|rowspan="6"|KEY_COL4
+
| rowspan="6" |KEY_COL4
−
|rowspan="6"|CPU.KEY_COL4
+
| rowspan="6" |CPU.KEY_COL4
−
|rowspan="6"|T6
+
| rowspan="6" |T6
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|FLEXCAN2_TX
 
|FLEXCAN2_TX
Line 1,005: Line 1,054:
 
|GPIO4_IO14
 
|GPIO4_IO14
 
|-
 
|-
−
|rowspan="6"|J2.107
+
| rowspan="6" |J2.107
−
|rowspan="6"|KEY_ROW4
+
| rowspan="6" |KEY_ROW4
−
|rowspan="6"|CPU.KEY_ROW4
+
| rowspan="6" |CPU.KEY_ROW4
−
|rowspan="6"|V5
+
| rowspan="6" |V5
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|FLEXCAN2_RX
 
|FLEXCAN2_RX
Line 1,370: Line 1,419:
 
|
 
|
 
|-
 
|-
−
|rowspan="7"|J2.177
+
| rowspan="7" |J2.177
−
|rowspan="7"|EIM_D19
+
| rowspan="7" |EIM_D19
−
|rowspan="7"|CPU.EIM_D19
+
| rowspan="7" |CPU.EIM_D19
−
|rowspan="7"|G21
+
| rowspan="7" |G21
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI1_SS1
 
|ECSPI1_SS1
Line 1,398: Line 1,447:
 
|EPDC_DATA12
 
|EPDC_DATA12
 
|-
 
|-
−
|rowspan="6"|J2.179
+
| rowspan="6" |J2.179
−
|rowspan="6"|EIM_D20
+
| rowspan="6" |EIM_D20
−
|rowspan="6"|CPU.EIM_D20
+
| rowspan="6" |CPU.EIM_D20
−
|rowspan="6"|G20
+
| rowspan="6" |G20
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI4_SS0
 
|ECSPI4_SS0
Line 1,423: Line 1,472:
 
|EPIT2_OUT
 
|EPIT2_OUT
 
|-
 
|-
−
|rowspan="7"|J2.181
+
| rowspan="7" |J2.181
−
|rowspan="7"|EIM_D21
+
| rowspan="7" |EIM_D21
−
|rowspan="7"|CPU.EIM_D21
+
| rowspan="7" |CPU.EIM_D21
−
|rowspan="7"|H20
+
| rowspan="7" |H20
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI4_SCLK
 
|ECSPI4_SCLK
Line 1,451: Line 1,500:
 
|SPDIF_IN
 
|SPDIF_IN
 
|-
 
|-
−
|rowspan="7"|J2.183
+
| rowspan="7" |J2.183
−
|rowspan="7"|EIM_D22
+
| rowspan="7" |EIM_D22
−
|rowspan="7"|CPU.EIM_D22
+
| rowspan="7" |CPU.EIM_D22
−
|rowspan="7"|E23
+
| rowspan="7" |E23
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI4_MISO
 
|ECSPI4_MISO
Line 1,479: Line 1,528:
 
|EPDC_SDCE6
 
|EPDC_SDCE6
 
|-
 
|-
−
|rowspan="8"|J2.185
+
| rowspan="8" |J2.185
−
|rowspan="8"|EIM_D23
+
| rowspan="8" |EIM_D23
−
|rowspan="8"|CPU.EIM_D23
+
| rowspan="8" |CPU.EIM_D23
−
|rowspan="8"|D25
+
| rowspan="8" |D25
−
|rowspan="8"|AXEL_IO_3V3
+
| rowspan="8" |AXEL_IO_3V3
−
|rowspan="8"|IO
+
| rowspan="8" |IO
−
|rowspan="8"|
+
| rowspan="8" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_DI0_D0_CS
 
|IPU1_DI0_D0_CS
Line 1,510: Line 1,559:
 
|EPDC_DATA11
 
|EPDC_DATA11
 
|-
 
|-
−
|rowspan="8"|J2.187
+
| rowspan="8" |J2.187
−
|rowspan="8"|EIM_D24
+
| rowspan="8" |EIM_D24
−
|rowspan="8"|CPU.EIM_D24
+
| rowspan="8" |CPU.EIM_D24
−
|rowspan="8"|F22
+
| rowspan="8" |F22
−
|rowspan="8"|AXEL_IO_3V3
+
| rowspan="8" |AXEL_IO_3V3
−
|rowspan="8"|IO
+
| rowspan="8" |IO
−
|rowspan="8"|
+
| rowspan="8" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI4_SS2
 
|ECSPI4_SS2
Line 1,541: Line 1,590:
 
|EPDC_SDCE7
 
|EPDC_SDCE7
 
|-
 
|-
−
|rowspan="8"|J2.189
+
| rowspan="8" |J2.189
−
|rowspan="8"|EIM_D25
+
| rowspan="8" |EIM_D25
−
|rowspan="8"|CPU.EIM_D25
+
| rowspan="8" |CPU.EIM_D25
−
|rowspan="8"|G22
+
| rowspan="8" |G22
−
|rowspan="8"|AXEL_IO_3V3
+
| rowspan="8" |AXEL_IO_3V3
−
|rowspan="8"|IO
+
| rowspan="8" |IO
−
|rowspan="8"|
+
| rowspan="8" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ECSPI4_SS3
 
|ECSPI4_SS3
Line 1,572: Line 1,621:
 
|EPDC_SDCE8
 
|EPDC_SDCE8
 
|-
 
|-
−
|rowspan="8"|J2.191
+
| rowspan="8" |J2.191
−
|rowspan="8"|EIM_D26
+
| rowspan="8" |EIM_D26
−
|rowspan="8"|CPU.EIM_D26
+
| rowspan="8" |CPU.EIM_D26
−
|rowspan="8"|E24
+
| rowspan="8" |E24
−
|rowspan="8"|AXEL_IO_3V3
+
| rowspan="8" |AXEL_IO_3V3
−
|rowspan="8"|IO
+
| rowspan="8" |IO
−
|rowspan="8"|
+
| rowspan="8" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_DI1_PIN11
 
|IPU1_DI1_PIN11
Line 1,603: Line 1,652:
 
|EPDC_SDOED
 
|EPDC_SDOED
 
|-
 
|-
−
|rowspan="8"|J2.193
+
| rowspan="8" |J2.193
−
|rowspan="8"|EIM_D27
+
| rowspan="8" |EIM_D27
−
|rowspan="8"|CPU.EIM_D27
+
| rowspan="8" |CPU.EIM_D27
−
|rowspan="8"|E25
+
| rowspan="8" |E25
−
|rowspan="8"|AXEL_IO_3V3
+
| rowspan="8" |AXEL_IO_3V3
−
|rowspan="8"|IO
+
| rowspan="8" |IO
−
|rowspan="8"|
+
| rowspan="8" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_DI1_PIN13
 
|IPU1_DI1_PIN13
Line 1,634: Line 1,683:
 
|EPDC_SDOE
 
|EPDC_SDOE
 
|-
 
|-
−
|rowspan="8"|J2.195
+
| rowspan="8" |J2.195
−
|rowspan="8"|EIM_D28
+
| rowspan="8" |EIM_D28
−
|rowspan="8"|CPU.EIM_D28
+
| rowspan="8" |CPU.EIM_D28
−
|rowspan="8"|G23
+
| rowspan="8" |G23
−
|rowspan="8"|AXEL_IO_3V3
+
| rowspan="8" |AXEL_IO_3V3
−
|rowspan="8"|IO
+
| rowspan="8" |IO
−
|rowspan="8"|
+
| rowspan="8" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|I2C1_SDA
 
|I2C1_SDA
Line 1,665: Line 1,714:
 
|EPDC_PWR_CTRL3
 
|EPDC_PWR_CTRL3
 
|-
 
|-
−
|rowspan="7"|J2.197
+
| rowspan="7" |J2.197
−
|rowspan="7"|EIM_D29
+
| rowspan="7" |EIM_D29
−
|rowspan="7"|CPU.EIM_D29
+
| rowspan="7" |CPU.EIM_D29
−
|rowspan="7"|J19
+
| rowspan="7" |J19
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_DI1_PIN15
 
|IPU1_DI1_PIN15
Line 1,693: Line 1,742:
 
|EPDC_PWR_WAKE
 
|EPDC_PWR_WAKE
 
|-
 
|-
−
|rowspan="7"|J2.199
+
| rowspan="7" |J2.199
−
|rowspan="7"|EIM_D30
+
| rowspan="7" |EIM_D30
−
|rowspan="7"|CPU.EIM_D30
+
| rowspan="7" |CPU.EIM_D30
−
|rowspan="7"|J20
+
| rowspan="7" |J20
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_DISP1_DATA21
 
|IPU1_DISP1_DATA21
Line 1,721: Line 1,770:
 
|EPDC_SDOEZ
 
|EPDC_SDOEZ
 
|-
 
|-
−
|rowspan="8"|J2.201
+
| rowspan="8" |J2.201
−
|rowspan="8"|EIM_D31
+
| rowspan="8" |EIM_D31
−
|rowspan="8"|CPU.EIM_D31
+
| rowspan="8" |CPU.EIM_D31
−
|rowspan="8"|H21
+
| rowspan="8" |H21
−
|rowspan="8"|AXEL_IO_3V3
+
| rowspan="8" |AXEL_IO_3V3
−
|rowspan="8"|IO
+
| rowspan="8" |IO
−
|rowspan="8"|
+
| rowspan="8" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_DISP1_DATA20
 
|IPU1_DISP1_DATA20
Line 1,764: Line 1,813:
 
|}
 
|}
  
−
=== Pinout Table EVEN pins declaration ===
+
== SODIMM EVEN pins declaration ==
  
 
{| class="wikitable"  
 
{| class="wikitable"  
Line 1,771: Line 1,820:
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Ball/pin #  
 
! latexfontsize="scriptsize" | Ball/pin #  
−
! latexfontsize="scriptsize" | Voltage|domain
+
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Notes  
 
! latexfontsize="scriptsize" | Notes  
Line 1,843: Line 1,892:
 
|
 
|
 
|
 
|
 +
* If this power supply is not used, the pin can be left open.
 +
* Even if this power supply is not used, NXP recommends to connect a capacitor. A 100nF capacitor is connected on the SoM.
 
|
 
|
 
|
 
|
Line 1,872: Line 1,923:
 
|
 
|
 
|
 
|
−
|
+
|This is a pulled-up input. Leave unconnected to select "1". Connect to ground to select "0". For more details, please see also the following pages:
 +
* [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Reset_scheme_and_control_signals | Reset scheme and control signals]]
 +
* [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/System_boot | System boot]]
 
|
 
|
 
|
 
|
 
|-
 
|-
 
|J2.22
 
|J2.22
−
|CPU_PORN
+
|CPU_PORn
−
|CPU.CPU_PORN
+
|CPU.CPU_PORn
 
|C11
 
|C11
 
|
 
|
Line 1,896: Line 1,949:
 
|
 
|
 
|-
 
|-
−
|rowspan="6"|J2.26
+
| rowspan="6" |J2.26
−
|rowspan="6"|GPIO_0
+
| rowspan="6" |GPIO_0
−
|rowspan="6"|CPU.GPIO_0
+
| rowspan="6" |CPU.GPIO_0
−
|rowspan="6"|T5
+
| rowspan="6" |T5
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|CCM_CLKO1
 
|CCM_CLKO1
Line 1,921: Line 1,974:
 
|SNVS_VIO_5
 
|SNVS_VIO_5
 
|-
 
|-
−
|rowspan="7"|J2.28
+
| rowspan="7" |J2.28
−
|rowspan="7"|GPIO_1
+
| rowspan="7" |GPIO_1
−
|rowspan="7"|CPU.GPIO_1
+
| rowspan="7" |CPU.GPIO_1
−
|rowspan="7"|T4
+
| rowspan="7" |T4
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |[[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#Handling_CPU-initiated_software_reset | Reset_scheme_and_control_signals#Handling_CPU-initiated_software_reset]]
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_RX_CLK
 
|ESAI_RX_CLK
Line 1,959: Line 2,012:
 
|
 
|
 
|-
 
|-
−
|rowspan="5"|J2.32
+
| rowspan="5" |J2.32
−
|rowspan="5"|GPIO_2
+
| rowspan="5" |GPIO_2
−
|rowspan="5"|CPU.GPIO_2
+
| rowspan="5" |CPU.GPIO_2
−
|rowspan="5"|T1
+
| rowspan="5" |T1
−
|rowspan="5"|AXEL_IO_3V3
+
| rowspan="5" |AXEL_IO_3V3
−
|rowspan="5"|IO
+
| rowspan="5" |IO
−
|rowspan="5"|
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_TX_FS
 
|ESAI_TX_FS
Line 1,981: Line 2,034:
 
|MLB_DATA
 
|MLB_DATA
 
|-
 
|-
−
|rowspan="7"|J2.34
+
| rowspan="7" |J2.34
−
|rowspan="7"|GPIO_3/I2C3_SCL
+
| rowspan="7" |GPIO_3/I2C3_SCL
−
|rowspan="7"|CPU.GPIO_3
+
| rowspan="7" |CPU.GPIO_3
−
|rowspan="7"|R7
+
| rowspan="7" |R7
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_RX_HF_CLK
 
|ESAI_RX_HF_CLK
Line 2,009: Line 2,062:
 
|MLB_CLK
 
|MLB_CLK
 
|-
 
|-
−
|rowspan="4"|J2.36
+
| rowspan="4" |J2.36
−
|rowspan="4"|GPIO_4
+
| rowspan="4" |GPIO_4
−
|rowspan="4"|CPU.GPIO_4
+
| rowspan="4" |CPU.GPIO_4
−
|rowspan="4"|R6
+
| rowspan="4" |R6
−
|rowspan="4"|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|rowspan="4"|IO
+
| rowspan="4" |IO
−
|rowspan="4"|
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_TX_HF_CLK
 
|ESAI_TX_HF_CLK
Line 2,028: Line 2,081:
 
|SD2_CD_B
 
|SD2_CD_B
 
|-
 
|-
−
|rowspan="6"|J2.38
+
| rowspan="6" |J2.38
−
|rowspan="6"|GPIO_5
+
| rowspan="6" |GPIO_5
−
|rowspan="6"|CPU.GPIO_5
+
| rowspan="6" |CPU.GPIO_5
−
|rowspan="6"|R4
+
| rowspan="6" |R4
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_TX2_RX3
 
|ESAI_TX2_RX3
Line 2,053: Line 2,106:
 
|ARM_EVENTI
 
|ARM_EVENTI
 
|-
 
|-
−
|rowspan="5"|J2.40
+
| rowspan="5" |J2.40
−
|rowspan="5"|GPIO_6/I2C3_SDA
+
| rowspan="5" |GPIO_6/I2C3_SDA
−
|rowspan="5"|CPU.GPIO_6
+
| rowspan="5" |CPU.GPIO_6
−
|rowspan="5"|T3
+
| rowspan="5" |T3
−
|rowspan="5"|AXEL_IO_3V3
+
| rowspan="5" |AXEL_IO_3V3
−
|rowspan="5"|IO
+
| rowspan="5" |IO
−
|rowspan="5"|
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_TX_CLK
 
|ESAI_TX_CLK
Line 2,075: Line 2,128:
 
|MLB_SIG
 
|MLB_SIG
 
|-
 
|-
−
|rowspan="9"|J2.42
+
| rowspan="9" |J2.42
−
|rowspan="9"|GPIO_7//FLEXCAN1_H
+
| rowspan="9" |GPIO_7//FLEXCAN1_H
−
|rowspan="9"|CPU.GPIO_7
+
| rowspan="9" |CPU.GPIO_7
−
|rowspan="9"|R3
+
| rowspan="9" |R3
−
|rowspan="9"|AXEL_IO_3V3
+
| rowspan="9" |AXEL_IO_3V3
−
|rowspan="9"|IO
+
| rowspan="9" |IO
−
|rowspan="9"| Hardware mounting option depending on order code|CAN_TX (PHY onboard) or GPIO_7
+
| rowspan="9" |<nowiki> Hardware mounting option depending on order code|CAN_TX (PHY onboard) or GPIO_7</nowiki>
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_TX4_RX1
 
|ESAI_TX4_RX1
Line 2,109: Line 2,162:
 
|I2C4_SCL
 
|I2C4_SCL
 
|-
 
|-
−
|rowspan="9"|J2.44
+
| rowspan="9" |J2.44
−
|rowspan="9"|GPIO_8//FLEXCAN1_L
+
| rowspan="9" |GPIO_8//FLEXCAN1_L
−
|rowspan="9"|CPU.GPIO_8
+
| rowspan="9" |CPU.GPIO_8
−
|rowspan="9"|R5
+
| rowspan="9" |R5
−
|rowspan="9"|AXEL_IO_3V3
+
| rowspan="9" |AXEL_IO_3V3
−
|rowspan="9"|IO
+
| rowspan="9" |IO
−
|rowspan="9"| Hardware mounting option depending on order code|CAN_RX (PHY onboard) or GPIO_8
+
| rowspan="9" |<nowiki> Hardware mounting option depending on order code|CAN_RX (PHY onboard) or GPIO_8</nowiki>
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_TX5_RX0
 
|ESAI_TX5_RX0
Line 2,143: Line 2,196:
 
|I2C4_SDA
 
|I2C4_SDA
 
|-
 
|-
−
|rowspan="7"|J2.46
+
| rowspan="7" |J2.46
−
|rowspan="7"|GPIO_9
+
| rowspan="7" |GPIO_9
−
|rowspan="7"|CPU.GPIO_9
+
| rowspan="7" |CPU.GPIO_9
−
|rowspan="7"|T2
+
| rowspan="7" |T2
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_RX_FS
 
|ESAI_RX_FS
Line 2,171: Line 2,224:
 
|SD1_WP
 
|SD1_WP
 
|-
 
|-
−
|rowspan="7"|J2.48
+
| rowspan="7" |J2.48
−
|rowspan="7"|GPIO_16
+
| rowspan="7" |GPIO_16
−
|rowspan="7"|CPU.GPIO_16
+
| rowspan="7" |CPU.GPIO_16
−
|rowspan="7"|R2
+
| rowspan="7" |R2
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_TX3_RX2
 
|ESAI_TX3_RX2
Line 2,199: Line 2,252:
 
|JTAG_DE_B
 
|JTAG_DE_B
 
|-
 
|-
−
|rowspan="6"|J2.50
+
| rowspan="6" |J2.50
−
|rowspan="6"|GPIO_17
+
| rowspan="6" |GPIO_17
−
|rowspan="6"|CPU.GPIO_17
+
| rowspan="6" |CPU.GPIO_17
−
|rowspan="6"|R1
+
| rowspan="6" |R1
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_TX0
 
|ESAI_TX0
Line 2,224: Line 2,277:
 
|GPIO7_IO12
 
|GPIO7_IO12
 
|-
 
|-
−
|rowspan="7"|J2.52
+
| rowspan="7" |J2.52
−
|rowspan="7"|GPIO_18
+
| rowspan="7" |GPIO_18
−
|rowspan="7"|CPU.GPIO_18
+
| rowspan="7" |CPU.GPIO_18
−
|rowspan="7"|P6
+
| rowspan="7" |P6
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|ESAI_TX1
 
|ESAI_TX1
Line 2,252: Line 2,305:
 
|SNVS_VIO_5_CTL
 
|SNVS_VIO_5_CTL
 
|-
 
|-
−
|rowspan="7"|J2.54
+
| rowspan="7" |J2.54
−
|rowspan="7"|GPIO_19
+
| rowspan="7" |GPIO_19
−
|rowspan="7"|CPU.GPIO_19
+
| rowspan="7" |CPU.GPIO_19
−
|rowspan="7"|P5
+
| rowspan="7" |P5
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|KEY_COL5
 
|KEY_COL5
 
|-
 
|-
−
|Pin ALT-2
+
|Pin ALT-1
 
|ENET_1588_EVENT0_OUT
 
|ENET_1588_EVENT0_OUT
 
|-
 
|-
−
|Pin ALT-3
+
|Pin ALT-2
 
|SPDIF_OUT
 
|SPDIF_OUT
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
 
|CCM_CLKO1
 
|CCM_CLKO1
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-4
 
|ECSPI1_RDY
 
|ECSPI1_RDY
 
|-
 
|-
−
|Pin ALT-6
+
|Pin ALT-5
 
|GPIO4_IO05
 
|GPIO4_IO05
 
|-
 
|-
−
|????????????
+
|Pin ALT-6
 
|ENET_TX_ER
 
|ENET_TX_ER
 
|-
 
|-
Line 2,290: Line 2,343:
 
|
 
|
 
|-
 
|-
−
|rowspan="3"|J2.58
+
| rowspan="3" |J2.58
−
|rowspan="3"|CSI0_PIXCLK
+
| rowspan="3" |CSI0_PIXCLK
−
|rowspan="3"|CPU.CSI0_PIXCLK
+
| rowspan="3" |CPU.CSI0_PIXCLK
−
|rowspan="3"|P1
+
| rowspan="3" |P1
−
|rowspan="3"|AXEL_IO_3V3
+
| rowspan="3" |AXEL_IO_3V3
−
|rowspan="3"|IO
+
| rowspan="3" |IO
−
|rowspan="3"|
+
| rowspan="3" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_PIXCLK
 
|IPU1_CSI0_PIXCLK
Line 2,306: Line 2,359:
 
|ARM_EVENTO
 
|ARM_EVENTO
 
|-
 
|-
−
|rowspan="4"|J2.60
+
| rowspan="4" |J2.60
−
|rowspan="4"|CSI0_MCLK
+
| rowspan="4" |CSI0_MCLK
−
|rowspan="4"|CPU.CSI0_MCLK
+
| rowspan="4" |CPU.CSI0_MCLK
−
|rowspan="4"|P4
+
| rowspan="4" |P4
−
|rowspan="4"|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|rowspan="4"|IO
+
| rowspan="4" |IO
−
|rowspan="4"|
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_HSYNC
 
|IPU1_CSI0_HSYNC
Line 2,325: Line 2,378:
 
|ARM_TRACE_CTL
 
|ARM_TRACE_CTL
 
|-
 
|-
−
|rowspan="4"|J2.62
+
| rowspan="4" |J2.62
−
|rowspan="4"|CSI0_VSYNC
+
| rowspan="4" |CSI0_VSYNC
−
|rowspan="4"|CPU.CSI0_VSYNC
+
| rowspan="4" |CPU.CSI0_VSYNC
−
|rowspan="4"|N2
+
| rowspan="4" |N2
−
|rowspan="4"|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|rowspan="4"|IO
+
| rowspan="4" |IO
−
|rowspan="4"|
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_VSYNC
 
|IPU1_CSI0_VSYNC
Line 2,344: Line 2,397:
 
|ARM_TRACE00
 
|ARM_TRACE00
 
|-
 
|-
−
|rowspan="4"|J2.64
+
| rowspan="4" |J2.64
−
|rowspan="4"|CSI0_DATA_EN
+
| rowspan="4" |CSI0_DATA_EN
−
|rowspan="4"|CPU.CSI0_DATA_EN
+
| rowspan="4" |CPU.CSI0_DATA_EN
−
|rowspan="4"|P3
+
| rowspan="4" |P3
−
|rowspan="4"|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|rowspan="4"|IO
+
| rowspan="4" |IO
−
|rowspan="4"|
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_DATA_EN
 
|IPU1_CSI0_DATA_EN
Line 2,363: Line 2,416:
 
|ARM_TRACE_CLK
 
|ARM_TRACE_CLK
 
|-
 
|-
−
|rowspan="8"|J2.66
+
| rowspan="7" |J2.66
−
|rowspan="8"|CSI0_DAT4
+
| rowspan="7" |CSI0_DAT4
−
|rowspan="8"|CPU.CSI0_DAT4
+
| rowspan="7" |CPU.CSI0_DAT4
−
|rowspan="8"|N1
+
| rowspan="7" |N1
−
|rowspan="8"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="8"|IO
+
| rowspan="7" |IO
−
|rowspan="8"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_DATA04
 
|IPU1_CSI0_DATA04
Line 2,387: Line 2,440:
 
|Pin ALT-5
 
|Pin ALT-5
 
|GPIO5_IO22
 
|GPIO5_IO22
−
|-
 
−
|Pin ALT-6
 
−
|?????????????
 
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
 
|ARM_TRACE01
 
|ARM_TRACE01
 
|-
 
|-
−
|rowspan="7"|J2.68
+
| rowspan="7" |J2.68
−
|rowspan="7"|CSI0_DAT5
+
| rowspan="7" |CSI0_DAT5
−
|rowspan="7"|CPU.CSI0_DAT5
+
| rowspan="7" |CPU.CSI0_DAT5
−
|rowspan="7"|P2
+
| rowspan="7" |P2
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_DATA05
 
|IPU1_CSI0_DATA05
Line 2,422: Line 2,472:
 
|ARM_TRACE02
 
|ARM_TRACE02
 
|-
 
|-
−
|rowspan="7"|J2.70
+
| rowspan="7" |J2.70
−
|rowspan="7"|CSI0_DAT6
+
| rowspan="7" |CSI0_DAT6
−
|rowspan="7"|CPU.CSI0_DAT6
+
| rowspan="7" |CPU.CSI0_DAT6
−
|rowspan="7"|N4
+
| rowspan="7" |N4
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_DATA06
 
|IPU1_CSI0_DATA06
Line 2,450: Line 2,500:
 
|ARM_TRACE03
 
|ARM_TRACE03
 
|-
 
|-
−
|rowspan="7"|J2.72
+
| rowspan="7" |J2.72
−
|rowspan="7"|CSI0_DAT7
+
| rowspan="7" |CSI0_DAT7
−
|rowspan="7"|CPU.CSI0_DAT7
+
| rowspan="7" |CPU.CSI0_DAT7
−
|rowspan="7"|N3
+
| rowspan="7" |N3
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_DATA07
 
|IPU1_CSI0_DATA07
Line 2,478: Line 2,528:
 
|ARM_TRACE04
 
|ARM_TRACE04
 
|-
 
|-
−
|rowspan="7"|J2.74
+
| rowspan="7" |J2.74
−
|rowspan="7"|CSI0_DAT8
+
| rowspan="7" |CSI0_DAT8
−
|rowspan="7"|CPU.CSI0_DAT8
+
| rowspan="7" |CPU.CSI0_DAT8
−
|rowspan="7"|N6
+
| rowspan="7" |N6
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_DATA08
 
|IPU1_CSI0_DATA08
Line 2,506: Line 2,556:
 
|ARM_TRACE05
 
|ARM_TRACE05
 
|-
 
|-
−
|rowspan="7"|J2.76
+
| rowspan="7" |J2.76
−
|rowspan="7"|CSI0_DAT9
+
| rowspan="7" |CSI0_DAT9
−
|rowspan="7"|CPU.CSI0_DAT9
+
| rowspan="7" |CPU.CSI0_DAT9
−
|rowspan="7"|N5
+
| rowspan="7" |N5
−
|rowspan="7"|AXEL_IO_3V3
+
| rowspan="7" |AXEL_IO_3V3
−
|rowspan="7"|IO
+
| rowspan="7" |IO
−
|rowspan="7"|
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_DATA09
 
|IPU1_CSI0_DATA09
Line 2,534: Line 2,584:
 
|ARM_TRACE06
 
|ARM_TRACE06
 
|-
 
|-
−
|rowspan="6"|J2.78
+
| rowspan="6" |J2.78
−
|rowspan="6"|CSI0_DAT10
+
| rowspan="6" |CSI0_DAT10
−
|rowspan="6"|CPU.CSI0_DAT10
+
| rowspan="6" |CPU.CSI0_DAT10
−
|rowspan="6"|M1
+
| rowspan="6" |M1
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_DATA10
 
|IPU1_CSI0_DATA10
Line 2,559: Line 2,609:
 
|ARM_TRACE07
 
|ARM_TRACE07
 
|-
 
|-
−
|rowspan="6"|J2.80
+
| rowspan="6" |J2.80
−
|rowspan="6"|CSI0_DAT11
+
| rowspan="6" |CSI0_DAT11
−
|rowspan="6"|CPU.CSI0_DAT11
+
| rowspan="6" |CPU.CSI0_DAT11
−
|rowspan="6"|M3
+
| rowspan="6" |M3
−
|rowspan="6"|AXEL_IO_3V3
+
| rowspan="6" |AXEL_IO_3V3
−
|rowspan="6"|IO
+
| rowspan="6" |IO
−
|rowspan="6"|
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|IPU1_CSI0_DATA11
 
|IPU1_CSI0_DATA11
Line 2,794: Line 2,844:
 
|
 
|
 
|-
 
|-
−
|J2.124
+
| rowspan="4" |J2.124
−
|DI0_PIN15
+
| rowspan="4" |DI0_PIN15
−
|CPU.DI0_PIN15
+
| rowspan="4" |CPU.DI0_PIN15
−
|N21
+
| rowspan="4" |N21
−
|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|IO
+
| rowspan="4" |IO
−
|
+
| rowspan="4" |
−
|
+
|Pin ALT-0
−
|
+
|IPU1_DI0_PIN15
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DI0_PIN15
 
|-
 
|-
−
|J2.126
+
|Pin ALT-2
−
|DI0_PIN4
+
|AUD6_TXC
−
|CPU.DI0_PIN4
 
−
|P25
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.128
+
|Pin ALT-5
−
|DI0_PIN3
+
|GPIO4_IO17
−
|CPU.DI0_PIN3
 
−
|N20
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.130
+
| rowspan="4" |J2.126
−
|DI0_PIN2
+
| rowspan="4" |DI0_PIN4
−
|CPU.DI0_PIN2
+
| rowspan="4" |CPU.DI0_PIN4
−
|N25
+
| rowspan="4" |P25
−
|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|IO
+
| rowspan="4" |IO
−
|
+
| rowspan="4" |
−
|
+
|Pin ALT-0
−
|
+
|IPU1_DI0_PIN04
 
|-
 
|-
−
|J2.132
+
|Pin ALT-1
−
|DI0_DISP_CLK
+
|IPU2_DI0_PIN04
−
|CPU.DI0_DISP_CLK
 
−
|N19
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.134
+
|Pin ALT-2
−
|DISP0_DAT0
+
|AUD6_RXD
−
|CPU.DISP0_DAT0
+
|-
−
|P24
+
|Pin ALT-5
−
|AXEL_IO_3V3
+
|GPIO4_IO20
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.136
+
| rowspan="4" |J2.128
−
|DISP0_DAT1
+
| rowspan="4" |DI0_PIN3
−
|CPU.DISP0_DAT1
+
| rowspan="4" |CPU.DI0_PIN3
−
|P22
+
| rowspan="4" |N20
−
|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|IO
+
| rowspan="4" |IO
−
|
+
| rowspan="4" |
−
|
+
|Pin ALT-0
−
|
+
|IPU1_DI0_PIN03
 
|-
 
|-
−
|J2.138
+
|Pin ALT-1
−
|DISP0_DAT2
+
|IPU2_DI0_PIN03
−
|CPU.DISP0_DAT2
 
−
|P23
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.140
+
|Pin ALT-2
−
|DISP0_DAT3
+
|AUD6_TXFS
−
|CPU.DISP0_DAT3
 
−
|P21
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.142
+
|Pin ALT-5
−
|DISP0_DAT4
+
|GPIO4_IO19
−
|CPU.DISP0_DAT4
 
−
|P20
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.144
+
| rowspan="4" |J2.130
−
|DISP0_DAT5
+
| rowspan="4" |DI0_PIN2
−
|CPU.DISP0_DAT5
+
| rowspan="4" |CPU.DI0_PIN2
−
|R25
+
| rowspan="4" |N25
−
|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|IO
+
| rowspan="4" |IO
−
|
+
| rowspan="4" |
−
|
+
|Pin ALT-0
−
|
+
|IPU1_DI0_PIN02
 
|-
 
|-
−
|J2.146
+
|Pin ALT-1
−
|DGND
+
|IPU2_DI0_PIN02
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.148
+
|Pin ALT-2
−
|DISP0_DAT6
+
|AUD6_TXD
−
|CPU.DISP0_DAT6
 
−
|R23
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.150
+
|Pin ALT-5
−
|DISP0_DAT7
+
|GPIO4_IO18
−
|CPU.DISP0_DAT7
 
−
|R24
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.152
+
| rowspan="3" |J2.132
−
|DISP0_DAT8
+
| rowspan="3" |DI0_DISP_CLK
−
|CPU.DISP0_DAT8
+
| rowspan="3" |CPU.DI0_DISP_CLK
−
|R22
+
| rowspan="3" |N19
−
|AXEL_IO_3V3
+
| rowspan="3" |AXEL_IO_3V3
−
|IO
+
| rowspan="3" |IO
−
|
+
| rowspan="3" |
−
|
+
|Pin ALT-0
−
|
+
|IPU1_DI0_DISP_CLK
 
|-
 
|-
−
|J2.154
+
|Pin ALT-1
−
|DISP0_DAT9
+
|IPU2_DI0_DISP_CLK
−
|CPU.DISP0_DAT9
 
−
|T25
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.156
+
|Pin ALT-5
−
|DISP0_DAT10
+
|GPIO4_IO16
−
|CPU.DISP0_DAT10
 
−
|R21
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.158
+
| rowspan="4" |J2.134
−
|DISP0_DAT11
+
| rowspan="4" |DISP0_DAT0
−
|CPU.DISP0_DAT11
+
| rowspan="4" |CPU.DISP0_DAT0
−
|T23
+
| rowspan="4" |P24
−
|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|IO
+
| rowspan="4" |IO
−
|
+
| rowspan="4" |
−
|
+
|Pin ALT-0
−
|
+
|IPU1_DISP0_DATA00
 
|-
 
|-
−
|J2.160
+
|Pin ALT-1
−
|DISP0_DAT12
+
|IPU2_DISP0_DATA00
−
|CPU.DISP0_DAT12
 
−
|T24
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.162
+
|Pin ALT-2
−
|DISP0_DAT13
+
|ECSPI3_SCLK
−
|CPU.DISP0_DAT13
 
−
|R20
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.164
+
|Pin ALT-5
−
|DGND
+
|GPIO4_IO21
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.166
+
| rowspan="4" |J2.136
−
|DISP0_DAT14
+
| rowspan="4" |DISP0_DAT1
−
|CPU.DISP0_DAT14
+
| rowspan="4" |CPU.DISP0_DAT1
−
|U25
+
| rowspan="4" |P22
−
|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|IO
+
| rowspan="4" |IO
−
|
+
| rowspan="4" |
−
|
+
|Pin ALT-0
−
|
+
|IPU1_DISP0_DATA01
 
|-
 
|-
−
|J2.168
+
|Pin ALT-1
−
|DISP0_DAT15
+
|IPU2_DISP0_DATA01
−
|CPU.DISP0_DAT15
 
−
|T22
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.170
+
|Pin ALT-2
−
|DISP0_DAT16
+
|ECSPI3_MOSI
−
|CPU.DISP0_DAT16
 
−
|T21
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.172
+
|Pin ALT-5
−
|DISP0_DAT17
+
|GPIO4_IO22
−
|CPU.DISP0_DAT17
 
−
|U24
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.174
+
| rowspan="4" |J2.138
−
|DISP0_DAT18
+
| rowspan="4" |DISP0_DAT2
−
|CPU.DISP0_DAT18
+
| rowspan="4" |CPU.DISP0_DAT2
−
|V25
+
| rowspan="4" |P23
−
|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|IO
+
| rowspan="4" |IO
−
|
+
| rowspan="4" |
−
|
+
|Pin ALT-0
−
|
+
|IPU1_DISP0_DATA02
 
|-
 
|-
−
|J2.176
+
|Pin ALT-1
−
|DISP0_DAT19
+
|IPU2_DISP0_DATA02
−
|CPU.DISP0_DAT19
 
−
|U23
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.178
+
|Pin ALT-2
−
|DISP0_DAT20
+
|ECSPI3_MISO
−
|CPU.DISP0_DAT20
 
−
|U22
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.180
+
|Pin ALT-5
−
|DISP0_DAT21
+
|GPIO4_IO23
−
|CPU.DISP0_DAT21
 
−
|T20
 
−
|AXEL_IO_3V3
 
−
|IO
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.182
+
| rowspan="4" |J2.140
−
|DISP0_DAT22
+
| rowspan="4" |DISP0_DAT3
−
|CPU.DISP0_DAT22
+
| rowspan="4" |CPU.DISP0_DAT3
−
|V24
+
| rowspan="4" |P21
−
|AXEL_IO_3V3
+
| rowspan="4" |AXEL_IO_3V3
−
|IO
+
| rowspan="4" |IO
−
|
+
| rowspan="4" |
−
|
+
|Pin ALT-0
−
|
+
|IPU1_DISP0_DATA03
 
|-
 
|-
−
|J2.184
+
|Pin ALT-1
−
|DISP0_DAT23
+
|IPU2_DISP0_DATA03
−
|CPU.DISP0_DAT23
+
|-
−
|W24
+
|Pin ALT-2
−
|AXEL_IO_3V3
+
|ECSPI3_SS0
−
|IO
+
|-
 +
|Pin ALT-5
 +
|GPIO4_IO24
 +
|-
 +
| rowspan="4" |J2.142
 +
| rowspan="4" |DISP0_DAT4
 +
| rowspan="4" |CPU.DISP0_DAT4
 +
| rowspan="4" |P20
 +
| rowspan="4" |AXEL_IO_3V3
 +
| rowspan="4" |IO
 +
| rowspan="4" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA04
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA04
 +
|-
 +
|Pin ALT-2
 +
|ECSPI3_SS1
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO25
 +
|-
 +
| rowspan="5" |J2.144
 +
| rowspan="5" |DISP0_DAT5
 +
| rowspan="5" |CPU.DISP0_DAT5
 +
| rowspan="5" |P24
 +
| rowspan="5" |AXEL_IO_3V3
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA05
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA05
 +
|-
 +
|Pin ALT-2
 +
|ECSPI3_SS2
 +
|-
 +
|Pin ALT-3
 +
|AUD6_RXFS
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO26
 +
|-
 +
|J2.146
 +
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J2.186
+
| rowspan="5" |J2.148
−
|USB_OTG_VBUS
+
| rowspan="5" |DISP0_DAT6
−
|CPU.USB_OTG_VBUS
+
| rowspan="5" |CPU.DISP0_DAT6
−
|E9
+
| rowspan="5" |R23
−
|
+
| rowspan="5" |AXEL_IO_3V3
−
|
+
| rowspan="5" |IO
−
|
+
| rowspan="5" |
−
|
+
|Pin ALT-0
−
|
+
|IPU1_DISP0_DATA06
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA06
 
|-
 
|-
−
|J2.188
+
|Pin ALT-2
−
|USB_H1_VBUS
+
|ECSPI3_SS3
−
|CPU.USB_H1_VBUS
 
−
|D10
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.190
+
|Pin ALT-3
−
|DGND
+
|AUD6_RXC
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.192
+
|Pin ALT-5
−
|ENET_RX_ER
+
|GPIO4_IO27
−
|CPU.ENET_RX_ER
 
−
|W23
 
−
|VCC_ENET_1V8
 
−
|IO
 
−
|This pin is 1V8 tolerant (i.e. must be connected to a 1V8 power domain)
 
−
|
 
−
|
 
 
|-
 
|-
−
|J2.194
+
| rowspan="4" |J2.150
−
|ENET_RXD0
+
| rowspan="4" |DISP0_DAT7
−
|CPU.ENET_RXD0
+
| rowspan="4" |CPU.DISP0_DAT7
−
|W21
+
| rowspan="4" |R24
−
|VCC_ENET_1V8
+
| rowspan="4" |AXEL_IO_3V3
−
|IO
+
| rowspan="4" |IO
−
|This pin is 1V8 tolerant (i.e. must be connected to a 1V8 power domain)
+
| rowspan="4" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA07
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA07
 +
|-
 +
|Pin ALT-2
 +
|ECSPI3_RDY
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO28
 +
|-
 +
| rowspan="5" |J2.152
 +
| rowspan="5" |DISP0_DAT8
 +
| rowspan="5" |CPU.DISP0_DAT8
 +
| rowspan="5" |R22
 +
| rowspan="5" |AXEL_IO_3V3
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA08
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA08
 +
|-
 +
|Pin ALT-2
 +
|PWM1_OUT
 +
|-
 +
|Pin ALT-3
 +
|WDOG1_B
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO29
 +
|-
 +
| rowspan="5" |J2.154
 +
| rowspan="5" |DISP0_DAT9
 +
| rowspan="5" |CPU.DISP0_DAT9
 +
| rowspan="5" |T25
 +
| rowspan="5" |AXEL_IO_3V3
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA09
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA09
 +
|-
 +
|Pin ALT-2
 +
|PWM2_OUT
 +
|-
 +
|Pin ALT-3
 +
|WDOG2_B
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO30
 +
|-
 +
| rowspan="3" |J2.156
 +
| rowspan="3" |DISP0_DAT10
 +
| rowspan="3" |CPU.DISP0_DAT10
 +
| rowspan="3" |R21
 +
| rowspan="3" |AXEL_IO_3V3
 +
| rowspan="3" |IO
 +
| rowspan="3" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA10
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA10
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO31
 +
|-
 +
| rowspan="3" |J2.158
 +
| rowspan="3" |DISP0_DAT11
 +
| rowspan="3" |CPU.DISP0_DAT11
 +
| rowspan="3" |T23
 +
| rowspan="3" |AXEL_IO_3V3
 +
| rowspan="3" |IO
 +
| rowspan="3" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA11
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA11
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO05
 +
|-
 +
| rowspan="3" |J2.160
 +
| rowspan="3" |DISP0_DAT12
 +
| rowspan="3" |CPU.DISP0_DAT12
 +
| rowspan="3" |T24
 +
| rowspan="3" |AXEL_IO_3V3
 +
| rowspan="3" |IO
 +
| rowspan="3" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA12
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA12
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO06
 +
|-
 +
| rowspan="4" |J2.162
 +
| rowspan="4" |DISP0_DAT13
 +
| rowspan="4" |CPU.DISP0_DAT13
 +
| rowspan="4" |R20
 +
| rowspan="4" |AXEL_IO_3V3
 +
| rowspan="4" |IO
 +
| rowspan="4" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA13
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA13
 +
|-
 +
|Pin ALT-3
 +
|AUD5_RXFS
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO07
 +
|-
 +
|J2.164
 +
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 +
|
 
|
 
|
 
|
 
|
 +
|-
 +
| rowspan="4" |J2.166
 +
| rowspan="4" |DISP0_DAT14
 +
| rowspan="4" |CPU.DISP0_DAT14
 +
| rowspan="4" |U25
 +
| rowspan="4" |AXEL_IO_3V3
 +
| rowspan="4" |IO
 +
| rowspan="4" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA14
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA14
 +
|-
 +
|Pin ALT-3
 +
|AUD5_RXC
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO08
 +
|-
 +
| rowspan="5" |J2.168
 +
| rowspan="5" |DISP0_DAT15
 +
| rowspan="5" |CPU.DISP0_DAT15
 +
| rowspan="5" |T22
 +
| rowspan="5" |AXEL_IO_3V3
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA15
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA15
 +
|-
 +
|Pin ALT-2
 +
|ECSPI1_SS1
 +
|-
 +
|Pin ALT-3
 +
|ECSPI2_SS1
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO09
 +
|-
 +
| rowspan="6" |J2.170
 +
| rowspan="6" |DISP0_DAT16
 +
| rowspan="6" |CPU.DISP0_DAT16
 +
| rowspan="6" |T21
 +
| rowspan="6" |AXEL_IO_3V3
 +
| rowspan="6" |IO
 +
| rowspan="6" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA16
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA16
 +
|-
 +
|Pin ALT-2
 +
|ECSPI2_MOSI
 +
|-
 +
|Pin ALT-3
 +
|AUD5_TXC
 +
|-
 +
|Pin ALT-4
 +
|SDMA_EXT_EVENT0
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO10
 +
|-
 +
| rowspan="6" |J2.172
 +
| rowspan="6" |DISP0_DAT17
 +
| rowspan="6" |CPU.DISP0_DAT17
 +
| rowspan="6" |U24
 +
| rowspan="6" |AXEL_IO_3V3
 +
| rowspan="6" |IO
 +
| rowspan="6" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA17
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA17
 +
|-
 +
|Pin ALT-2
 +
|ECSPI2_MISO
 +
|-
 +
|Pin ALT-3
 +
|AUD5_TXD
 +
|-
 +
|Pin ALT-4
 +
|SDMA_EXT_EVENT1
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO11
 +
|-
 +
| rowspan="6" |J2.174
 +
| rowspan="6" |DISP0_DAT18
 +
| rowspan="6" |CPU.DISP0_DAT18
 +
| rowspan="6" |V25
 +
| rowspan="6" |AXEL_IO_3V3
 +
| rowspan="6" |IO
 +
| rowspan="6" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA18
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA18
 +
|-
 +
|Pin ALT-2
 +
|ECSPI2_SS0
 +
|-
 +
|Pin ALT-3
 +
|AUD5_TXFS
 +
|-
 +
|Pin ALT-4
 +
|AUD4_RXFS
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO12
 +
|-
 +
| rowspan="6" |J2.176
 +
| rowspan="6" |DISP0_DAT19
 +
| rowspan="6" |CPU.DISP0_DAT19
 +
| rowspan="6" |U23
 +
| rowspan="6" |AXEL_IO_3V3
 +
| rowspan="6" |IO
 +
| rowspan="6" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA19
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA19
 +
|-
 +
|Pin ALT-2
 +
|ECSPI2_SCLK
 +
|-
 +
|Pin ALT-3
 +
|AUD5_RXD
 +
|-
 +
|Pin ALT-4
 +
|AUD4_RXC
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO13
 +
|-
 +
| rowspan="5" |J2.178
 +
| rowspan="5" |DISP0_DAT20
 +
| rowspan="5" |CPU.DISP0_DAT20
 +
| rowspan="5" |U22
 +
| rowspan="5" |AXEL_IO_3V3
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA20
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA20
 +
|-
 +
|Pin ALT-2
 +
|ECSPI1_SCLK
 +
|-
 +
|Pin ALT-3
 +
|AUD4_TXC
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO14
 +
|-
 +
| rowspan="5" |J2.180
 +
| rowspan="5" |DISP0_DAT21
 +
| rowspan="5" |CPU.DISP0_DAT21
 +
| rowspan="5" |T20
 +
| rowspan="5" |AXEL_IO_3V3
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA21
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA21
 +
|-
 +
|Pin ALT-2
 +
|ECSPI1_MOSI
 +
|-
 +
|Pin ALT-3
 +
|AUD4_TXD
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO15
 +
|-
 +
| rowspan="5" |J2.182
 +
| rowspan="5" |DISP0_DAT22
 +
| rowspan="5" |CPU.DISP0_DAT22
 +
| rowspan="5" |V24
 +
| rowspan="5" |AXEL_IO_3V3
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA22
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA22
 +
|-
 +
|Pin ALT-2
 +
|ECSPI1_MISO
 +
|-
 +
|Pin ALT-3
 +
|AUD4_TXFS
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO16
 +
|-
 +
| rowspan="5" |J2.184
 +
| rowspan="5" |DISP0_DAT23
 +
| rowspan="5" |CPU.DISP0_DAT23
 +
| rowspan="5" |W24
 +
| rowspan="5" |AXEL_IO_3V3
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|IPU1_DISP0_DATA23
 +
|-
 +
|Pin ALT-1
 +
|IPU2_DISP0_DATA23
 +
|-
 +
|Pin ALT-2
 +
|ECSPI1_SS0
 +
|-
 +
|Pin ALT-3
 +
|AUD4_RXD
 +
|-
 +
|Pin ALT-5
 +
|GPIO5_IO17
 +
|-
 +
|J2.186
 +
|USB_OTG_VBUS
 +
|CPU.USB_OTG_VBUS
 +
|E9
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|-
 +
|J2.188
 +
|USB_H1_VBUS
 +
|CPU.USB_H1_VBUS
 +
|D10
 +
|
 +
|
 +
|
 +
|
 +
|
 +
|-
 +
|J2.190
 +
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 +
|
 +
|
 +
|
 +
|-
 +
| rowspan="6" |J2.192
 +
| rowspan="6" |ENET_RX_ER
 +
| rowspan="6" |CPU.ENET_RX_ER
 +
| rowspan="6" |W23
 +
| rowspan="6" |VCC_ENET_1V8
 +
| rowspan="6" |IO
 +
| rowspan="6" |This pin is 1V8 tolerant (i.e. must be connected to a 1V8 power domain)
 +
|Pin ALT-0
 +
|USB_OTG_ID
 +
|-
 +
|Pin ALT-1
 +
|ENET_RX_ER
 +
|-
 +
|Pin ALT-2
 +
|ESAI_RX_HF_CLK
 +
|-
 +
|Pin ALT-3
 +
|SPDIF_IN
 +
|-
 +
|Pin ALT-4
 +
|ENET_1588_EVENT2_OUT
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO24
 +
 +
|-
 +
| rowspan="4" |J2.194
 +
| rowspan="4" |ENET_RXD0
 +
| rowspan="4" |CPU.ENET_RXD0
 +
| rowspan="4" |W21
 +
| rowspan="4" |VCC_ENET_1V8
 +
| rowspan="4" |IO
 +
| rowspan="4" |This pin is 1V8 tolerant (i.e. must be connected to a 1V8 power domain)
 +
|Pin ALT-1
 +
|ENET_RX_DATA0
 +
|-
 +
|Pin ALT-2
 +
|ESAI_TX_HF_CLK
 +
|-
 +
|Pin ALT-3
 +
|SPDIF_OUT
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO27
 
|-
 
|-
 
|J2.196
 
|J2.196

Latest revision as of 17:11, 8 January 2024

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History
Issue Date Notes

2020/12/18

New documentation layout

2021/11/17

More details about BOOT_MODE_SEL signal
2021/11/26 Voltage domains legend added. Fixed the "Type" field of ETH0_LED1 and ETH0_LED2.


Connectors and Pinout Table[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on AXEL Lite SOM:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM DDR3 edge connector 204 pin TE Connectivity 2-2013289-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AXEL Lite pinout specifications. See the images below for reference:

AXEL Lite TOP view
AXEL Lite BOTTOM view

Pinout table naming conventions[edit | edit source]

This chapter contains the pinout description of the AXEL Lite SOM module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AxelLite connectors
Internal
connections 		Connections to the components
  • CPU.<x> : pin connected to CPU pad named <x>
  • CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232)
  • PMIC.<x> : pin connected to the Power Manager IC (NXP MMPF0100)
  • LAN.<x> : pin connected to the LAN PHY (Microchip KSZ9031)
  • NOR.<x>: pin connected to the flash NOR
  • SV.<x>: pin connected to voltage supervisor
  • MTR: pin connected to voltage monitors
Ball/pin # Component ball/pin number connected to signal
Voltage domain The voltage domain the pin belongs to
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • Pin ALT-1
  • Pin ALT-2
  • Pin ALT-3
  • Pin ALT-4
  • Pin ALT-5
  • Pin ALT-6
  • Pin ALT-7
  • Pin ALT-8

Voltage domains[edit | edit source]

Voltage domain Nominal voltage [V] Notes
3.3VIN 3.3 See Operational_characteristics of the SoM wiki page
VCC_ENET_1V8 1.8 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
AXEL_IO_3V3 3.3 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
GEN_2V5 2.5 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page

SODIMM ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage

domain

Type Notes Alternative Functions
J2.1 DGND DGND - - G
J2.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J2.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J2.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J2.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J2.11 DGND DGND - - G
J2.13 ETH0_LED1 LAN.LED1/PME_N1 17 VCC_ENET_1V8 O Internal 10k pull-up to 1.8V

This signal requires voltage level shifters if used at 3.3V

J2.15 ETH0_LED2 LAN.LED2 15 VCC_ENET_1V8 O Internal 10k pull-up to 1.8V

This signal requires voltage level shifters if used at 3.3V

J2.17 DGND DGND - - G
J2.19 ETH0_TXRX0_P LAN.TXRXP_A 2 AXEL_IO_3V3 D
J2.21 ETH0_TXRX0_M LAN.TXRXM_A 3 AXEL_IO_3V3 D
J2.23 ETH0_TXRX1_P LAN.TXRXP_B 5 AXEL_IO_3V3 D
J2.25 ETH0_TXRX1_M LAN.TXRXM_B 6 AXEL_IO_3V3 D
J2.27 ETH0_TXRX2_P LAN.TXRXP_C 7 AXEL_IO_3V3 D
J2.29 ETH0_TXRX2_M LAN.TXRXM_C 8 AXEL_IO_3V3 D
J2.31 ETH0_TXRX3_P LAN.TXRXP_D 10 AXEL_IO_3V3 D
J2.33 ETH0_TXRX3_M LAN.TXRXM_D 11 AXEL_IO_3V3 D
J2.35 DGND DGND - - G
J2.37 SD3_RST CPU.SD3_RST D15 AXEL_IO_3V3 IO Pin ALT-0 SD3_RESET
Pin ALT-1 UART3_RTS_B
Pin ALT-5 GPIO7_IO08
J2.39 SD3_DATA0 CPU.SD3_DATA0 E14 AXEL_IO_3V3 IO Pin ALT-0 SD3_DATA0
Pin ALT-1 UART1_CTS_B
Pin ALT-2 FLEXCAN2_TX
Pin ALT-5 GPIO7_IO04
J2.41 SD3_DATA1 CPU.SD3_DATA1 F14 AXEL_IO_3V3 IO Pin ALT-0 SD3_DATA1
Pin ALT-1 UART1_RTS_B
Pin ALT-2 FLEXCAN2_RX
Pin ALT-5 GPIO7_IO05
J2.43 SD3_DATA2 CPU.SD3_DATA2 A15 AXEL_IO_3V3 IO Pin ALT-0 SD3_DATA2
Pin ALT-5 GPIO7_IO06
J2.45 SD3_DATA3 CPU.SD3_DATA3 B15 AXEL_IO_3V3 IO Pin ALT-0 SD3_DATA3
Pin ALT-1 UART3_CTS_B
Pin ALT-5 GPIO7_IO07
J2.47 SD3_DATA4 CPU.SD3_DATA4 D13 AXEL_IO_3V3 IO Pin ALT-0 SD3_DATA4
Pin ALT-1 UART2_RX_DATA
Pin ALT-5 GPIO7_IO01
J2.49 SD3_DATA5 CPU.SD3_DATA5 C13 AXEL_IO_3V3 IO Pin ALT-0 SD3_DATA5
Pin ALT-1 UART2_TX_DATA
Pin ALT-5 GPIO7_IO00
J2.51 SD3_DATA6 CPU.SD3_DATA6 E13 AXEL_IO_3V3 IO Pin ALT-0 SD3_DATA6
Pin ALT-1 UART1_RX_DATA
Pin ALT-5 GPIO6_IO18
J2.53 SD3_DATA7 CPU.SD3_DATA7 F13 AXEL_IO_3V3 IO Pin ALT-0 SD3_DATA7
Pin ALT-1 UART1_TX_DATA
Pin ALT-5 GPIO6_IO17
J2.55 SD3_CMD CPU.SD3_CMD B13 AXEL_IO_3V3 IO Pin ALT-0 SD3_CMD
Pin ALT-1 UART2_CTS_B
Pin ALT-2 FLEXCAN1_TX
Pin ALT-5 GPIO7_IO02
J2.57 DGND DGND - - G
J2.59 SD3_CLK CPU.SD3_CLK D14 AXEL_IO_3V3 IO Pin ALT-0 SD3_CLK
Pin ALT-1 UART2_RTS_B
Pin ALT-2 UART2_RTS_B
Pin ALT-5 GPIO7_IO03
J2.61 SD2_DATA0 CPU.SD2_DATA0 A22 AXEL_IO_3V3 IO Pin ALT-0 SD2_DATA0
Pin ALT-1 ECSPI5_MISO
Pin ALT-3 AUD4_RXD
Pin ALT-4 KEY_ROW7
Pin ALT-5 GPIO1_IO15
Pin ALT-6 DCIC2_OUT
J2.63 SD2_DATA1 CPU.SD2_DATA1 E20 AXEL_IO_3V3 IO Pin ALT-0 SD2_DATA1
Pin ALT-1 ECSPI5_SS0
Pin ALT-2 EIM_CS2
Pin ALT-3 AUD4_TXFS
Pin ALT-4 KEY_COL7
Pin ALT-5 GPIO1_IO14
J2.65 SD2_DATA2 CPU.SD2_DATA2 A23 AXEL_IO_3V3 IO Pin ALT-0 SD2_DATA2
Pin ALT-1 ECSPI5_SS1
Pin ALT-2 EIM_CS3
Pin ALT-3 AUD4_TXD
Pin ALT-4 KEY_ROW6
Pin ALT-5 GPIO1_IO13
J2.67 SD2_DATA3 CPU.SD2_DATA3 B22 AXEL_IO_3V3 IO Pin ALT-0 SD2_DATA3
Pin ALT-1 ECSPI5_SS3
Pin ALT-2 ECSPI5_SS3
Pin ALT-3 AUD4_TXC
Pin ALT-5 GPIO1_IO12
J2.69 SD2_CMD CPU.SD2_CMD F19 AXEL_IO_3V3 IO Pin ALT-0 SD2_CMD
Pin ALT-1 ECSPI5_MOSI
Pin ALT-2 KEY_ROW5
Pin ALT-3 AUD4_RXC
Pin ALT-5 GPIO1_IO11
J2.71 SD2_CLK CPU.SD2_CLK C21 AXEL_IO_3V3 IO Pin ALT-0 SD2_CLK
Pin ALT-1 ECSPI5_SCLK
Pin ALT-2 KEY_COL5
Pin ALT-3 AUD4_RXFS
Pin ALT-5 GPIO1_IO10
J2.73 DGND DGND - - G
J2.75 SD1_DAT0 CPU.SD1_DAT0 A21 AXEL_IO_3V3 IO Pin ALT-0 SD1_DATA0
Pin ALT-1 ECSPI5_MISO
Pin ALT-2 GPT_CAPTURE1
Pin ALT-5 GPIO1_IO16
J2.77 SD1_DAT1 CPU.SD1_DAT1 C20 AXEL_IO_3V3 IO Pin ALT-0 SD1_DATA1
Pin ALT-1 ECSPI5_SS0
Pin ALT-2 PWM3_OUT
Pin ALT-3 GPT_CAPTURE2
Pin ALT-5 GPIO1_IO17
J2.79 SD1_DAT2 CPU.SD1_DAT2 E19 AXEL_IO_3V3 IO Pin ALT-0 SD1_DATA2
Pin ALT-1 ECSPI5_SS1
Pin ALT-2 GPT_COMPARE2
Pin ALT-3 PWM2_OUT
Pin ALT-4 WDOG1_B
Pin ALT-5 GPIO1_IO19
Pin ALT-6 WDOG1_RESET_B_DEB
J2.81 SD1_DAT3 CPU.SD1_DAT3 F18 AXEL_IO_3V3 IO Pin ALT-0 SD1_DATA3
Pin ALT-1 ECSPI5_SS2
Pin ALT-2 GPT_COMPARE3
Pin ALT-3 PWM1_OUT
Pin ALT-4 WDOG2_B
Pin ALT-5 GPIO1_IO21
Pin ALT-6 WDOG2_RESET_B_DEB
J2.83 SD1_CMD CPU.SD1_CMD B21 AXEL_IO_3V3 IO Pin ALT-0 SD1_CMD
Pin ALT-1 ECSPI5_MOSI
Pin ALT-2 PWM4_OUT
Pin ALT-3 GPT_COMPARE1
Pin ALT-5 GPIO1_IO18
J2.85 SD1_CLK CPU.SD1_CLK D20 AXEL_IO_3V3 IO Pin ALT-0 SD1_CLK
Pin ALT-1 ECSPI5_SCLK
Pin ALT-3 GPT_CLKIN
Pin ALT-5 GPIO1_IO20
J2.87 DGND DGND - - G
J2.89 KEY_COL0/|ECSPI1_SCLK CPU.KEY_COL0 W5 AXEL_IO_3V3 IO Pin ALT-0 ECSPI1_SCLK
Pin ALT-1 ENET_RX_DATA3
Pin ALT-2 AUD5_TXC
Pin ALT-3 KEY_COL0
Pin ALT-4 UART4_TX_DATA
Pin ALT-5 GPIO4_IO06
Pin ALT-6 DCIC1_OUT
J2.91 KEY_ROW0/|ECSPI1_MOSI CPU.KEY_ROW0 V6 AXEL_IO_3V3 IO Pin ALT-0 ECSPI1_MOSI
Pin ALT-1 ENET_TX_DATA3
Pin ALT-2 AUD5_TXD
Pin ALT-3 KEY_ROW0
Pin ALT-4 UART4_RX_DATA
Pin ALT-5 GPIO4_IO07
Pin ALT-6 DCIC2_OUT
J2.93 KEY_COL1/|ECSPI1_MISO CPU.KEY_COL1 U7 AXEL_IO_3V3 IO Pin ALT-0 ECSPI1_MISO
Pin ALT-1 ENET_MDIO
Pin ALT-2 AUD5_TXFS
Pin ALT-3 KEY_COL1
Pin ALT-4 UART5_TX_DATA
Pin ALT-5 GPIO4_IO08
Pin ALT-6 SD1_VSELECT
J2.95 KEY_ROW1/|ECSPI1_SS0 CPU.KEY_ROW1 U6 AXEL_IO_3V3 IO Pin ALT-0 ECSPI1_SS0
Pin ALT-1 ENET_COL
Pin ALT-2 AUD5_RXD
Pin ALT-3 KEY_ROW1
Pin ALT-4 UART5_RX_DATA
Pin ALT-5 GPIO4_IO09
Pin ALT-6 SD2_VSELECT
J2.97 KEY_COL2/|ECSPI1_SS1 CPU.KEY_COL2 W6 AXEL_IO_3V3 IO Pin ALT-0 ECSPI1_SS1
Pin ALT-1 ENET_RX_DATA2
Pin ALT-2 FLEXCAN1_TX
Pin ALT-3 KEY_COL2
Pin ALT-4 ENET_MDC
Pin ALT-5 GPIO4_IO10
Pin ALT-6 USB_H1_PWR_CTL_WAKE
J2.99 KEY_ROW2 CPU.KEY_ROW2 W4 AXEL_IO_3V3 IO Pin ALT-0 ECSPI1_SS2
Pin ALT-1 ENET_TX_DATA2
Pin ALT-2 FLEXCAN1_RX
Pin ALT-3 KEY_ROW2
Pin ALT-4 SD2_VSELECT
Pin ALT-5 GPIO4_IO11
Pin ALT-6 HDMI_TX_CEC_LINE
J2.101 KEY_COL3/|I2C2_SCL CPU.KEY_COL3 U5 AXEL_IO_3V3 IO Internally connected to PMIC I2C interface Pin ALT-0 ECSPI1_SS3
Pin ALT-1 ENET_CRS
Pin ALT-3 HDMI_TX_DDC_SCL
Pin ALT-4 KEY_COL3
Pin ALT-4 I2C2_SCL
Pin ALT-5 GPIO4_IO12
Pin ALT-6 SPDIF_IN
J2.103 KEY_ROW3/|I2C2_SDA CPU.KEY_ROW3 T7 AXEL_IO_3V3 IO Internally connected to PMIC I2C interface Pin ALT-1 ASRC_EXT_CLK
Pin ALT-2 HDMI_TX_DDC_SDA
Pin ALT-3 KEY_ROW3
Pin ALT-4 I2C2_SDA
Pin ALT-5 GPIO4_IO13
Pin ALT-6 SD1_VSELECT
J2.105 KEY_COL4 CPU.KEY_COL4 T6 AXEL_IO_3V3 IO Pin ALT-0 FLEXCAN2_TX
Pin ALT-1 IPU1_SISG4
Pin ALT-2 USB_OTG_OC
Pin ALT-3 KEY_COL4
Pin ALT-4 UART5_RTS_B
Pin ALT-5 GPIO4_IO14
J2.107 KEY_ROW4 CPU.KEY_ROW4 V5 AXEL_IO_3V3 IO Pin ALT-0 FLEXCAN2_RX
Pin ALT-1 IPU1_SISG5
Pin ALT-2 USB_OTG_PWR
Pin ALT-3 KEY_ROW4
Pin ALT-4 UART5_CTS_B
Pin ALT-5 GPIO4_IO15
J2.109 DGND DGND - - G
J2.111 HDMI_CLKN CPU.HDMI_CLKN J5 GEN_2V5 D
J2.113 HDMI_CLKP CPU.HDMI_CLKP J6 GEN_2V5 D
J2.115 HDMI_D0N CPU.HDMI_D0N K5 GEN_2V5 D
J2.117 HDMI_D0P CPU.HDMI_D0P K6 GEN_2V5 D
J2.119 HDMI_D1N CPU.HDMI_D1N J3 GEN_2V5 D
J2.121 HDMI_D1P CPU.HDMI_D1P J4 GEN_2V5 D
J2.123 HDMI_D2N CPU.HDMI_D2N K3 GEN_2V5 D
J2.125 HDMI_D2P CPU.HDMI_D2P K4 GEN_2V5 D
J2.127 HDMI_CEC_IN CPU.HDMI_DDCCEC K2 GEN_2V5 D
J2.129 HDMI_HPD CPU.HDMI_HPD K1 GEN_2V5 D
J2.131 DGND DGND - - G
J2.133 LVDS0_CLK_N CPU.LVDS0_CLK_N V4 GEN_2V5 D
J2.135 LVDS0_CLK_P CPU.LVDS0_CLK_P V3 GEN_2V5 D
J2.137 LVDS0_TX0_N CPU.LVDS0_TX0_N U2 GEN_2V5 D
J2.139 LVDS0_TX0_P CPU.LVDS0_TX0_P U1 GEN_2V5 D
J2.141 LVDS0_TX1_N CPU.LVDS0_TX1_N U4 GEN_2V5 D
J2.143 LVDS0_TX1_P CPU.LVDS0_TX1_P U3 GEN_2V5 D
J2.145 LVDS0_TX2_N CPU.LVDS0_TX2_N V2 GEN_2V5 D
J2.147 LVDS0_TX2_P CPU.LVDS0_TX2_P V1 GEN_2V5 D
J2.149 LVDS0_TX3_N CPU.LVDS0_TX3_N W2 GEN_2V5 D
J2.151 LVDS0_TX3_P CPU.LVDS0_TX3_P W1 GEN_2V5 D
J2.153 DGND DGND - - G
J2.155 LVDS1_CLK_N CPU.LVDS1_CLK_N Y3 GEN_2V5 D
J2.157 LVDS1_CLK_P CPU.LVDS1_CLK_P Y4 GEN_2V5 D
J2.159 LVDS1_TX0_N CPU.LVDS1_TX0_N Y1 GEN_2V5 D
J2.161 LVDS1_TX0_P CPU.LVDS1_TX0_P Y2 GEN_2V5 D
J2.163 LVDS1_TX1_N CPU.LVDS1_TX1_N AA2 GEN_2V5 D
J2.165 LVDS1_TX1_P CPU.LVDS1_TX1_P AA1 GEN_2V5 D
J2.167 LVDS1_TX2_N CPU.LVDS1_TX2_N AB1 GEN_2V5 D
J2.169 LVDS1_TX2_P CPU.LVDS1_TX2_P AB2 GEN_2V5 D
J2.171 LVDS1_TX3_N CPU.LVDS1_TX3_N AA3 GEN_2V5 D
J2.173 LVDS1_TX3_P CPU.LVDS1_TX3_P AA4 GEN_2V5 D
J2.175 DGND DGND - - G
J2.177 EIM_D19 CPU.EIM_D19 G21 AXEL_IO_3V3 IO Pin ALT-0 ECSPI1_SS1
Pin ALT-1 IPU1_DI0_PIN08
Pin ALT-2 IPU2_CSI1_DATA16
Pin ALT-3 UART1_CTS_B
Pin ALT-4 GPIO3_IO19
Pin ALT-5 EPIT1_OUT
Pin ALT-7 EPDC_DATA12
J2.179 EIM_D20 CPU.EIM_D20 G20 AXEL_IO_3V3 IO Pin ALT-0 ECSPI4_SS0
Pin ALT-1 IPU1_DI0_PIN16
Pin ALT-2 IPU2_CSI1_DATA15
Pin ALT-3 UART1_RTS_B
Pin ALT-4 GPIO3_IO20
Pin ALT-5 EPIT2_OUT
J2.181 EIM_D21 CPU.EIM_D21 H20 AXEL_IO_3V3 IO Pin ALT-0 ECSPI4_SCLK
Pin ALT-1 IPU1_DI0_PIN17
Pin ALT-2 IPU2_CSI1_DATA11
Pin ALT-3 USB_OTG_OC
Pin ALT-4 GPIO3_IO21
Pin ALT-5 I2C1_SCL
Pin ALT-6 SPDIF_IN
J2.183 EIM_D22 CPU.EIM_D22 E23 AXEL_IO_3V3 IO Pin ALT-0 ECSPI4_MISO
Pin ALT-1 IPU1_DI0_PIN01
Pin ALT-2 IPU2_CSI1_DATA10
Pin ALT-3 USB_OTG_PWR
Pin ALT-4 GPIO3_IO22
Pin ALT-5 SPDIF_OUT
Pin ALT-7 EPDC_SDCE6
J2.185 EIM_D23 CPU.EIM_D23 D25 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DI0_D0_CS
Pin ALT-1 UART3_CTS_B
Pin ALT-2 UART1_DCD_B
Pin ALT-3 IPU2_CSI1_DATA_EN
Pin ALT-4 GPIO3_IO23
Pin ALT-5 IPU1_DI1_PIN02
Pin ALT-6 IPU1_DI1_PIN14
Pin ALT-7 EPDC_DATA11
J2.187 EIM_D24 CPU.EIM_D24 F22 AXEL_IO_3V3 IO Pin ALT-0 ECSPI4_SS2
Pin ALT-1 UART3_TX_DATA
Pin ALT-2 ECSPI1_SS2
Pin ALT-3 ECSPI2_SS2
Pin ALT-4 GPIO3_IO24
Pin ALT-5 AUD5_RXFS
Pin ALT-6 UART1_DTR_B
Pin ALT-7 EPDC_SDCE7
J2.189 EIM_D25 CPU.EIM_D25 G22 AXEL_IO_3V3 IO Pin ALT-0 ECSPI4_SS3
Pin ALT-1 UART3_RX_DATA
Pin ALT-2 ECSPI1_SS3
Pin ALT-3 ECSPI2_SS3
Pin ALT-4 GPIO3_IO25
Pin ALT-5 AUD5_RXC
Pin ALT-6 UART1_DSR_B
Pin ALT-7 EPDC_SDCE8
J2.191 EIM_D26 CPU.EIM_D26 E24 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DI1_PIN11
Pin ALT-1 IPU1_CSI0_DATA01
Pin ALT-2 IPU2_CSI1_DATA14
Pin ALT-3 UART2_TX_DATA
Pin ALT-4 GPIO3_IO26
Pin ALT-5 IPU1_SISG2
Pin ALT-6 IPU1_DISP1_DATA22
Pin ALT-7 EPDC_SDOED
J2.193 EIM_D27 CPU.EIM_D27 E25 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DI1_PIN13
Pin ALT-1 IPU1_CSI0_DATA00
Pin ALT-2 IPU2_CSI1_DATA13
Pin ALT-3 UART2_RX_DATA
Pin ALT-4 GPIO3_IO27
Pin ALT-5 IPU1_SISG3
Pin ALT-6 IPU1_DISP1_DATA23
Pin ALT-7 EPDC_SDOE
J2.195 EIM_D28 CPU.EIM_D28 G23 AXEL_IO_3V3 IO Pin ALT-0 I2C1_SDA
Pin ALT-1 ECSPI4_MOSI
Pin ALT-2 IPU2_CSI1_DATA12
Pin ALT-3 UART2_CTS_B
Pin ALT-4 GPIO3_IO28
Pin ALT-5 IPU1_EXT_TRIG
Pin ALT-6 IPU1_DI0_PIN13
Pin ALT-7 EPDC_PWR_CTRL3
J2.197 EIM_D29 CPU.EIM_D29 J19 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DI1_PIN15
Pin ALT-1 ECSPI4_SS0
Pin ALT-3 UART2_RTS_B
Pin ALT-4 GPIO3_IO29
Pin ALT-5 IPU2_CSI1_VSYNC
Pin ALT-6 IPU1_DI0_PIN14
Pin ALT-7 EPDC_PWR_WAKE
J2.199 EIM_D30 CPU.EIM_D30 J20 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP1_DATA21
Pin ALT-1 IPU1_DI0_PIN11
Pin ALT-2 IPU1_CSI0_DATA03
Pin ALT-3 UART3_CTS_B
Pin ALT-4 GPIO3_IO30
Pin ALT-5 USB_H1_OC
Pin ALT-7 EPDC_SDOEZ
J2.201 EIM_D31 CPU.EIM_D31 H21 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP1_DATA20
Pin ALT-1 IPU1_DI0_PIN12
Pin ALT-2 IPU1_CSI0_DATA02
Pin ALT-3 UART3_RTS_B
Pin ALT-4 GPIO3_IO31
Pin ALT-5 USB_H1_PWR
Pin ALT-7 EPDC_SDCLK_P
Pin ALT-8 EIM_ACLK_FREERUN
J2.203 DGND DGND - - G

SODIMM EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J2.2 DGND DGND - - G
J2.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J2.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J2.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J2.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J2.12 DGND DGND - - G
J2.14 PMIC_LICELL PMIC.LICELL 42
  • If this power supply is not used, the pin can be left open.
  • Even if this power supply is not used, NXP recommends to connect a capacitor. A 100nF capacitor is connected on the SoM.
J2.16 CPU_ONOFF CPU.CPU_ONOFF D12
J2.18 BOARD_PGOOD - -
J2.20 BOOT_MODE_SEL BOOT MODE SELECTION This is a pulled-up input. Leave unconnected to select "1". Connect to ground to select "0". For more details, please see also the following pages:
J2.22 CPU_PORn CPU.CPU_PORn C11
J2.24 PMIC_PWRON PMIC.PWRON 56
J2.26 GPIO_0 CPU.GPIO_0 T5 AXEL_IO_3V3 IO Pin ALT-0 CCM_CLKO1
Pin ALT-2 KEY_COL5
Pin ALT-3 ASRC_EXT_CLK
Pin ALT-5 GPIO1_IO00
Pin ALT-6 USB_H1_PWR
Pin ALT-7 SNVS_VIO_5
J2.28 GPIO_1 CPU.GPIO_1 T4 AXEL_IO_3V3 IO Reset_scheme_and_control_signals#Handling_CPU-initiated_software_reset Pin ALT-0 ESAI_RX_CLK
Pin ALT-1 WDOG2_B
Pin ALT-2 KEY_ROW5
Pin ALT-3 USB_OTG_ID
Pin ALT-4 PWM2_OUT
Pin ALT-5 GPIO1_IO01
Pin ALT-6 SD1_CD_B
J2.30 DGND DGND - - G
J2.32 GPIO_2 CPU.GPIO_2 T1 AXEL_IO_3V3 IO Pin ALT-0 ESAI_TX_FS
Pin ALT-2 KEY_ROW6
Pin ALT-5 GPIO1_IO02
Pin ALT-6 SD2_WP
Pin ALT-7 MLB_DATA
J2.34 GPIO_3/I2C3_SCL CPU.GPIO_3 R7 AXEL_IO_3V3 IO Pin ALT-0 ESAI_RX_HF_CLK
Pin ALT-2 I2C3_SCL
Pin ALT-3 XTALOSC_REF_CLK_24M
Pin ALT-4 CCM_CLKO2
Pin ALT-5 GPIO1_IO03
Pin ALT-6 USB_H1_OC
Pin ALT-7 MLB_CLK
J2.36 GPIO_4 CPU.GPIO_4 R6 AXEL_IO_3V3 IO Pin ALT-0 ESAI_TX_HF_CLK
Pin ALT-2 KEY_COL7
Pin ALT-5 GPIO1_IO04
Pin ALT-6 SD2_CD_B
J2.38 GPIO_5 CPU.GPIO_5 R4 AXEL_IO_3V3 IO Pin ALT-0 ESAI_TX2_RX3
Pin ALT-2 KEY_ROW7
Pin ALT-3 CCM_CLKO1
Pin ALT-5 GPIO1_IO05
Pin ALT-6 I2C3_SCL
Pin ALT-7 ARM_EVENTI
J2.40 GPIO_6/I2C3_SDA CPU.GPIO_6 T3 AXEL_IO_3V3 IO Pin ALT-0 ESAI_TX_CLK
Pin ALT-2 I2C3_SDA
Pin ALT-5 GPIO1_IO06
Pin ALT-6 SD2_LCTL
Pin ALT-7 MLB_SIG
J2.42 GPIO_7//FLEXCAN1_H CPU.GPIO_7 R3 AXEL_IO_3V3 IO Hardware mounting option depending on order code|CAN_TX (PHY onboard) or GPIO_7 Pin ALT-0 ESAI_TX4_RX1
Pin ALT-1 ECSPI5_RDY
Pin ALT-2 EPIT1_OUT
Pin ALT-3 FLEXCAN1_TX
Pin ALT-4 UART2_TX_DATA
Pin ALT-5 GPIO1_IO07
Pin ALT-6 SPDIF_LOCK
Pin ALT-7 USB_OTG_HOST_MODE
Pin ALT-8 I2C4_SCL
J2.44 GPIO_8//FLEXCAN1_L CPU.GPIO_8 R5 AXEL_IO_3V3 IO Hardware mounting option depending on order code|CAN_RX (PHY onboard) or GPIO_8 Pin ALT-0 ESAI_TX5_RX0
Pin ALT-1 XTALOSC_REF_CLK_32K
Pin ALT-2 EPIT2_OUT
Pin ALT-3 FLEXCAN1_RX
Pin ALT-4 UART2_RX_DATA
Pin ALT-5 GPIO1_IO08
Pin ALT-6 SPDIF_SR_CLK
Pin ALT-7 USB_OTG_PWR_CTL_WAKE
Pin ALT-8 I2C4_SDA
J2.46 GPIO_9 CPU.GPIO_9 T2 AXEL_IO_3V3 IO Pin ALT-0 ESAI_RX_FS
Pin ALT-1 WDOG1_B
Pin ALT-2 KEY_COL6
Pin ALT-3 CCM_REF_EN_B
Pin ALT-4 PWM1_OUT
Pin ALT-5 GPIO1_IO09
Pin ALT-6 SD1_WP
J2.48 GPIO_16 CPU.GPIO_16 R2 AXEL_IO_3V3 IO Pin ALT-0 ESAI_TX3_RX2
Pin ALT-1 ENET_1588_EVENT2_IN
Pin ALT-2 ENET_REF_CLK
Pin ALT-4 SPDIF_IN
Pin ALT-5 GPIO7_IO11
Pin ALT-6 I2C3_SDA
Pin ALT-7 JTAG_DE_B
J2.50 GPIO_17 CPU.GPIO_17 R1 AXEL_IO_3V3 IO Pin ALT-0 ESAI_TX0
Pin ALT-1 ENET_1588_EVENT3_IN
Pin ALT-2 CCM_PMIC_READY
Pin ALT-3 SDMA_EXT_EVENT0
Pin ALT-4 SPDIF_OUT
Pin ALT-5 GPIO7_IO12
J2.52 GPIO_18 CPU.GPIO_18 P6 AXEL_IO_3V3 IO Pin ALT-0 ESAI_TX1
Pin ALT-1 ENET_RX_CLK
Pin ALT-2 SD3_VSELECT
Pin ALT-3 SDMA_EXT_EVENT1
Pin ALT-4 ASRC_EXT_CLK
Pin ALT-5 GPIO7_IO13
Pin ALT-6 SNVS_VIO_5_CTL
J2.54 GPIO_19 CPU.GPIO_19 P5 AXEL_IO_3V3 IO Pin ALT-0 KEY_COL5
Pin ALT-1 ENET_1588_EVENT0_OUT
Pin ALT-2 SPDIF_OUT
Pin ALT-3 CCM_CLKO1
Pin ALT-4 ECSPI1_RDY
Pin ALT-5 GPIO4_IO05
Pin ALT-6 ENET_TX_ER
J2.56 DGND DGND - - G
J2.58 CSI0_PIXCLK CPU.CSI0_PIXCLK P1 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_PIXCLK
Pin ALT-5 GPIO5_IO18
Pin ALT-7 ARM_EVENTO
J2.60 CSI0_MCLK CPU.CSI0_MCLK P4 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_HSYNC
Pin ALT-3 CCM_CLKO1
Pin ALT-5 GPIO5_IO19
Pin ALT-7 ARM_TRACE_CTL
J2.62 CSI0_VSYNC CPU.CSI0_VSYNC N2 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_VSYNC
Pin ALT-1 EIM_DATA01
Pin ALT-5 GPIO5_IO21
Pin ALT-7 ARM_TRACE00
J2.64 CSI0_DATA_EN CPU.CSI0_DATA_EN P3 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_DATA_EN
Pin ALT-1 EIM_DATA00
Pin ALT-5 GPIO5_IO20
Pin ALT-7 ARM_TRACE_CLK
J2.66 CSI0_DAT4 CPU.CSI0_DAT4 N1 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_DATA04
Pin ALT-1 EIM_DATA02
Pin ALT-2 ECSPI1_SCLK
Pin ALT-3 KEY_COL5
Pin ALT-4 AUD3_TXC
Pin ALT-5 GPIO5_IO22
Pin ALT-7 ARM_TRACE01
J2.68 CSI0_DAT5 CPU.CSI0_DAT5 P2 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_DATA05
Pin ALT-1 EIM_DATA03
Pin ALT-2 ECSPI1_MOSI
Pin ALT-3 KEY_ROW5
Pin ALT-4 AUD3_TXD
Pin ALT-5 GPIO5_IO23
Pin ALT-7 ARM_TRACE02
J2.70 CSI0_DAT6 CPU.CSI0_DAT6 N4 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_DATA06
Pin ALT-1 EIM_DATA04
Pin ALT-2 ECSPI1_MISO
Pin ALT-3 KEY_COL6
Pin ALT-4 AUD3_TXFS
Pin ALT-5 GPIO5_IO24
Pin ALT-7 ARM_TRACE03
J2.72 CSI0_DAT7 CPU.CSI0_DAT7 N3 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_DATA07
Pin ALT-1 EIM_DATA05
Pin ALT-2 ECSPI1_SS0
Pin ALT-3 KEY_ROW6
Pin ALT-4 AUD3_RXD
Pin ALT-5 GPIO5_IO25
Pin ALT-7 ARM_TRACE04
J2.74 CSI0_DAT8 CPU.CSI0_DAT8 N6 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_DATA08
Pin ALT-1 EIM_DATA06
Pin ALT-2 ECSPI2_SCLK
Pin ALT-3 KEY_COL7
Pin ALT-4 I2C1_SDA
Pin ALT-5 GPIO5_IO26
Pin ALT-7 ARM_TRACE05
J2.76 CSI0_DAT9 CPU.CSI0_DAT9 N5 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_DATA09
Pin ALT-1 EIM_DATA07
Pin ALT-2 ECSPI2_MOSI
Pin ALT-3 KEY_ROW7
Pin ALT-4 I2C1_SCL
Pin ALT-5 GPIO5_IO27
Pin ALT-7 ARM_TRACE06
J2.78 CSI0_DAT10 CPU.CSI0_DAT10 M1 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_DATA10
Pin ALT-1 AUD3_RXC
Pin ALT-2 ECSPI2_MISO
Pin ALT-3 UART1_TX_DATA
Pin ALT-5 GPIO5_IO28
Pin ALT-7 ARM_TRACE07
J2.80 CSI0_DAT11 CPU.CSI0_DAT11 M3 AXEL_IO_3V3 IO Pin ALT-0 IPU1_CSI0_DATA11
Pin ALT-1 AUD3_RXFS
Pin ALT-2 ECSPI2_SS0
Pin ALT-3 UART1_RX_DATA
Pin ALT-5 GPIO5_IO29
Pin ALT-7 ARM_TRACE08
J2.82 DGND DGND - - G
J2.84 CLK1_N CPU.CLK1_N C7 GEN_2V5 D
J2.86 CLK1_P CPU.CLK1_P D7 GEN_2V5 D
J2.88 CLK2_N CPU.CLK2_N C5 GEN_2V5 D
J2.90 CLK2_P CPU.CLK2_P D5 GEN_2V5 D
J2.92 PCIE_RXN CPU.PCIE_RXN B1 GEN_2V5 D
J2.94 PCIE_RXP CPU.PCIE_RXP B2 GEN_2V5 D
J2.96 PCIE_TXN CPU.PCIE_TXN A3 GEN_2V5 D
J2.98 PCIE_TXP CPU.PCIE_TXP B3 GEN_2V5 D
J2.100 DGND DGND - - G
J2.102 CSI_CLK0M CPU.CSI_CLK0M F4 GEN_2V5 D
J2.104 CSI_CLK0P CPU.CSI_CLK0P F3 GEN_2V5 D
J2.106 CSI_D0M CPU.CSI_D0M E4 GEN_2V5 D
J2.108 CSI_D0P CPU.CSI_D0P E3 GEN_2V5 D
J2.110 CSI_D1M CPU.CSI_D1M D1 GEN_2V5 D
J2.112 CSI_D1P CPU.CSI_D1P D2 GEN_2V5 D
J2.114 CSI_D2M CPU.CSI_D2M E1 GEN_2V5 D
J2.116 CSI_D2P CPU.CSI_D2P E2 GEN_2V5 D
J2.118 CSI_D3M CPU.CSI_D3M F2 GEN_2V5 D
J2.120 CSI_D3P CPU.CSI_D3P F1 GEN_2V5 D
J2.122 DGND DGND - - G
J2.124 DI0_PIN15 CPU.DI0_PIN15 N21 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DI0_PIN15
Pin ALT-1 IPU2_DI0_PIN15
Pin ALT-2 AUD6_TXC
Pin ALT-5 GPIO4_IO17
J2.126 DI0_PIN4 CPU.DI0_PIN4 P25 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DI0_PIN04
Pin ALT-1 IPU2_DI0_PIN04
Pin ALT-2 AUD6_RXD
Pin ALT-5 GPIO4_IO20
J2.128 DI0_PIN3 CPU.DI0_PIN3 N20 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DI0_PIN03
Pin ALT-1 IPU2_DI0_PIN03
Pin ALT-2 AUD6_TXFS
Pin ALT-5 GPIO4_IO19
J2.130 DI0_PIN2 CPU.DI0_PIN2 N25 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DI0_PIN02
Pin ALT-1 IPU2_DI0_PIN02
Pin ALT-2 AUD6_TXD
Pin ALT-5 GPIO4_IO18
J2.132 DI0_DISP_CLK CPU.DI0_DISP_CLK N19 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DI0_DISP_CLK
Pin ALT-1 IPU2_DI0_DISP_CLK
Pin ALT-5 GPIO4_IO16
J2.134 DISP0_DAT0 CPU.DISP0_DAT0 P24 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA00
Pin ALT-1 IPU2_DISP0_DATA00
Pin ALT-2 ECSPI3_SCLK
Pin ALT-5 GPIO4_IO21
J2.136 DISP0_DAT1 CPU.DISP0_DAT1 P22 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA01
Pin ALT-1 IPU2_DISP0_DATA01
Pin ALT-2 ECSPI3_MOSI
Pin ALT-5 GPIO4_IO22
J2.138 DISP0_DAT2 CPU.DISP0_DAT2 P23 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA02
Pin ALT-1 IPU2_DISP0_DATA02
Pin ALT-2 ECSPI3_MISO
Pin ALT-5 GPIO4_IO23
J2.140 DISP0_DAT3 CPU.DISP0_DAT3 P21 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA03
Pin ALT-1 IPU2_DISP0_DATA03
Pin ALT-2 ECSPI3_SS0
Pin ALT-5 GPIO4_IO24
J2.142 DISP0_DAT4 CPU.DISP0_DAT4 P20 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA04
Pin ALT-1 IPU2_DISP0_DATA04
Pin ALT-2 ECSPI3_SS1
Pin ALT-5 GPIO4_IO25
J2.144 DISP0_DAT5 CPU.DISP0_DAT5 P24 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA05
Pin ALT-1 IPU2_DISP0_DATA05
Pin ALT-2 ECSPI3_SS2
Pin ALT-3 AUD6_RXFS
Pin ALT-5 GPIO4_IO26
J2.146 DGND DGND - - G
J2.148 DISP0_DAT6 CPU.DISP0_DAT6 R23 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA06
Pin ALT-1 IPU2_DISP0_DATA06
Pin ALT-2 ECSPI3_SS3
Pin ALT-3 AUD6_RXC
Pin ALT-5 GPIO4_IO27
J2.150 DISP0_DAT7 CPU.DISP0_DAT7 R24 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA07
Pin ALT-1 IPU2_DISP0_DATA07
Pin ALT-2 ECSPI3_RDY
Pin ALT-5 GPIO4_IO28
J2.152 DISP0_DAT8 CPU.DISP0_DAT8 R22 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA08
Pin ALT-1 IPU2_DISP0_DATA08
Pin ALT-2 PWM1_OUT
Pin ALT-3 WDOG1_B
Pin ALT-5 GPIO4_IO29
J2.154 DISP0_DAT9 CPU.DISP0_DAT9 T25 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA09
Pin ALT-1 IPU2_DISP0_DATA09
Pin ALT-2 PWM2_OUT
Pin ALT-3 WDOG2_B
Pin ALT-5 GPIO4_IO30
J2.156 DISP0_DAT10 CPU.DISP0_DAT10 R21 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA10
Pin ALT-1 IPU2_DISP0_DATA10
Pin ALT-5 GPIO4_IO31
J2.158 DISP0_DAT11 CPU.DISP0_DAT11 T23 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA11
Pin ALT-1 IPU2_DISP0_DATA11
Pin ALT-5 GPIO5_IO05
J2.160 DISP0_DAT12 CPU.DISP0_DAT12 T24 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA12
Pin ALT-1 IPU2_DISP0_DATA12
Pin ALT-5 GPIO5_IO06
J2.162 DISP0_DAT13 CPU.DISP0_DAT13 R20 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA13
Pin ALT-1 IPU2_DISP0_DATA13
Pin ALT-3 AUD5_RXFS
Pin ALT-5 GPIO5_IO07
J2.164 DGND DGND - - G
J2.166 DISP0_DAT14 CPU.DISP0_DAT14 U25 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA14
Pin ALT-1 IPU2_DISP0_DATA14
Pin ALT-3 AUD5_RXC
Pin ALT-5 GPIO5_IO08
J2.168 DISP0_DAT15 CPU.DISP0_DAT15 T22 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA15
Pin ALT-1 IPU2_DISP0_DATA15
Pin ALT-2 ECSPI1_SS1
Pin ALT-3 ECSPI2_SS1
Pin ALT-5 GPIO5_IO09
J2.170 DISP0_DAT16 CPU.DISP0_DAT16 T21 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA16
Pin ALT-1 IPU2_DISP0_DATA16
Pin ALT-2 ECSPI2_MOSI
Pin ALT-3 AUD5_TXC
Pin ALT-4 SDMA_EXT_EVENT0
Pin ALT-5 GPIO5_IO10
J2.172 DISP0_DAT17 CPU.DISP0_DAT17 U24 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA17
Pin ALT-1 IPU2_DISP0_DATA17
Pin ALT-2 ECSPI2_MISO
Pin ALT-3 AUD5_TXD
Pin ALT-4 SDMA_EXT_EVENT1
Pin ALT-5 GPIO5_IO11
J2.174 DISP0_DAT18 CPU.DISP0_DAT18 V25 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA18
Pin ALT-1 IPU2_DISP0_DATA18
Pin ALT-2 ECSPI2_SS0
Pin ALT-3 AUD5_TXFS
Pin ALT-4 AUD4_RXFS
Pin ALT-5 GPIO5_IO12
J2.176 DISP0_DAT19 CPU.DISP0_DAT19 U23 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA19
Pin ALT-1 IPU2_DISP0_DATA19
Pin ALT-2 ECSPI2_SCLK
Pin ALT-3 AUD5_RXD
Pin ALT-4 AUD4_RXC
Pin ALT-5 GPIO5_IO13
J2.178 DISP0_DAT20 CPU.DISP0_DAT20 U22 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA20
Pin ALT-1 IPU2_DISP0_DATA20
Pin ALT-2 ECSPI1_SCLK
Pin ALT-3 AUD4_TXC
Pin ALT-5 GPIO5_IO14
J2.180 DISP0_DAT21 CPU.DISP0_DAT21 T20 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA21
Pin ALT-1 IPU2_DISP0_DATA21
Pin ALT-2 ECSPI1_MOSI
Pin ALT-3 AUD4_TXD
Pin ALT-5 GPIO5_IO15
J2.182 DISP0_DAT22 CPU.DISP0_DAT22 V24 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA22
Pin ALT-1 IPU2_DISP0_DATA22
Pin ALT-2 ECSPI1_MISO
Pin ALT-3 AUD4_TXFS
Pin ALT-5 GPIO5_IO16
J2.184 DISP0_DAT23 CPU.DISP0_DAT23 W24 AXEL_IO_3V3 IO Pin ALT-0 IPU1_DISP0_DATA23
Pin ALT-1 IPU2_DISP0_DATA23
Pin ALT-2 ECSPI1_SS0
Pin ALT-3 AUD4_RXD
Pin ALT-5 GPIO5_IO17
J2.186 USB_OTG_VBUS CPU.USB_OTG_VBUS E9
J2.188 USB_H1_VBUS CPU.USB_H1_VBUS D10
J2.190 DGND DGND - - G
J2.192 ENET_RX_ER CPU.ENET_RX_ER W23 VCC_ENET_1V8 IO This pin is 1V8 tolerant (i.e. must be connected to a 1V8 power domain) Pin ALT-0 USB_OTG_ID
Pin ALT-1 ENET_RX_ER
Pin ALT-2 ESAI_RX_HF_CLK
Pin ALT-3 SPDIF_IN
Pin ALT-4 ENET_1588_EVENT2_OUT
Pin ALT-5 GPIO1_IO24
J2.194 ENET_RXD0 CPU.ENET_RXD0 W21 VCC_ENET_1V8 IO This pin is 1V8 tolerant (i.e. must be connected to a 1V8 power domain) Pin ALT-1 ENET_RX_DATA0
Pin ALT-2 ESAI_TX_HF_CLK
Pin ALT-3 SPDIF_OUT
Pin ALT-5 GPIO1_IO27
J2.196 USB_OTG_DN CPU.USB_OTG_DN B6 D
J2.198 USB_OTG_DP CPU.USB_OTG_DP A6 D
J2.200 USB_HOST_DP CPU.USB_HOST_DP E10 D
J2.202 USB_HOST_DN CPU.USB_HOST_DN F10 D
J2.204 DGND DGND - - G
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