ONDA SOM/ONDA Hardware/Pinout Table
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| 2026/03/09 | First documentation | ||
Contents
Connectors and Pinout Table[edit | edit source]
This chapter contains the pinout description of the ONDA module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin ONDA connectors.
Connectors description[edit | edit source]
In the following table are described the interface connectors on ONDA SOM:
| Connector name | Connector Type | Notes | Carrier board counterpart |
|---|---|---|---|
| J1, J2, J3 | Hirose FX8C-140S-SV 3x140 pins 0.6mm pitch connectors |
Hirose FX8C-140P-SV<x>
where <x> stays for:
|
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference:
Pinout table naming conventions[edit | edit source]
Each row in the pinout tables contains the following information:
- CPU.<x> : pin connected to CPU (processing system) pad named <x>
- FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
- CAN.<x> : pin connected to the CAN transceiver
TCAN3413DR - LAN.<x> : pin connected to the LAN PHY
LAN8830 - USB.<x> : pin connected to the USB transceiver
USB3317C - EEPROM.<x>: pin connected to the EEPROM
24LC32AT - RTC.<x>: pin connected to the Real Time Clock
DS3232MZ+ - WD.<x>: pin connected to the Watchdog
MAX6373KA+
| Pin | reference to the connector pin |
| Pin Name | Pin (signal) name on the ONDA connectors |
| Internal connections |
Connections to the ONDA components |
| Ball/pin # | Component ball/pin number connected to signal |
| Voltage | I/O voltage levels
|
| Type | Pin type
|
SOM J1 ODD pins (1 to 139) declaration[edit | edit source]
| Pin | Pin Name | Internal Connections | Ball/pin # | Supply Group | Type | Voltage | Note |
| J1.1 | DGND | DGND | - | - | G | - | Digital ground |
| J1.3 | IO_T0U_N12_VRP_65 | FPGA.IO_T0U_N12_VRP_65 | W9 | Bank 65 | I/O | User defined | |
| J1.5 | IO_L23P_T3U_N8_I2C_SCLK_65 | FPGA.IO_L23P_T3U_N8_I2C_SCLK_65 | K9 | Bank 65 | I/O | User defined | |
| J1.7 | IO_L23N_T3U_N9_65 | FPGA.IO_L23N_T3U_N9_65 | J9 | Bank 65 | I/O | User defined | |
| J1.9 | IO_L21P_T3L_N4_AD8P_65 | FPGA.IO_L21P_T3L_N4_AD8P_65 | J7 | Bank 65 | I/O | User defined | |
| J1.11 | IO_L21N_T3L_N5_AD8N_65 | FPGA.IO_L21N_T3L_N5_AD8N_65 | H7 | Bank 65 | I/O | User defined | |
| J1.13 | DGND | DGND | - | - | - | - | Digital ground |
| J1.15 | IO_L19P_T3L_N0_DBC_AD9P_65 | FPGA.IO_L19P_T3L_N0_DBC_AD9P_65 | J5 | Bank 65 | I/O | User defined | |
| J1.17 | IO_L19N_T3L_N1_DBC_AD9N_65 | FPGA.IO_L19N_T3L_N1_DBC_AD9N_65 | J4 | Bank 65 | I/O | User defined | |
| J1.19 | DGND | DGND | - | - | G | - | Digital ground |
| J1.21 | IO_L17P_T2U_N8_AD10P_65 | FPGA.IO_L17P_T2U_N8_AD10P_65 | N9 | Bank 65 | I/O | User defined | |
| J1.23 | IO_L17N_T2U_N9_AD10N_65 | FPGA.IO_L17N_T2U_N9_AD10N_65 | N8 | Bank 65 | I/O | User defined | |
| J1.25 | IO_L15P_T2L_N4_AD11P_65 | FPGA.IO_L15P_T2L_N4_AD11P_65 | N7 | Bank 65 | I/O | User defined | |
| J1.27 | IO_L15N_T2L_N5_AD11N_65 | FPGA.IO_L15N_T2L_N5_AD11N_65 | N6 | Bank 65 | I/O | User defined | |
| J1.29 | DGND | DGND | - | - | G | - | Digital ground |
| J1.31 | IO_L13P_T2L_N0_GC_QBC_65 | FPGA.IO_L13P_T2L_N0_GC_QBC_65 | L7 | Bank 65 | I/O | User defined | |
| J1.33 | IO_L13N_T2L_N1_GC_QBC_65 | FPGA.IO_L13N_T2L_N1_GC_QBC_65 | L6 | Bank 35 | I/O | User defined | |
| J1.35 | DGND | DGND | - | - | G | - | Digital ground |
| J1.37 | IO_L11P_T1U_N8_GC_65 | FPGA.IO_L11P_T1U_N8_GC_65 | K4 | Bank 65 | I/O | User defined | |
| J1.39 | IO_L11N_T1U_N9_GC_65 | FPGA.IO_L11N_T1U_N9_GC_65 | K3 | Bank 65 | I/O | User defined | |
| J1.41 | IO_L9P_T1L_N4_AD12P_65 | FPGA.IO_L9P_T1L_N4_AD12P_65 | K2 | Bank 65 | I/O | User defined | |
| J1.43 | IO_L9N_T1L_N5_AD12N_65 | FPGA.IO_L9N_T1L_N5_AD12N_65 | J2 | Bank 65 | I/O | User defined | |
| J1.45 | IO_L7P_T1L_N0_QBC_AD13P_65 | FPGA.IO_L7P_T1L_N0_QBC_AD13P_65 | L1 | Bank 65 | I/O | User defined | |
| J1.47 | IO_L7N_T1L_N1_QBC_AD13N_65 | FPGA.IO_L7N_T1L_N1_QBC_AD13N_65 | K1 | Bank 65 | I/O | User defined | |
| J1.49 | DGND | DGND | - | - | G | - | Digital ground |
| J1.51 | IO_L5P_T0U_N8_AD14P_65 | FPGA.IO_L5P_T0U_N8_AD14P_65 | R7 | Bank 65 | I/O | User defined | |
| J1.53 | IO_L5N_T0U_N9_AD14N_65 | FPGA.IO_L5N_T0U_N9_AD14N_65 | T7 | Bank 65 | I/O | User defined | |
| J1.55 | IO_L3P_T0L_N4_AD15P_65 | FPGA.IO_L3P_T0L_N4_AD15P_65 | U8 | Bank 65 | I/O | User defined | |
| J1.57 | IO_L3N_T0L_N5_AD15N_65 | FPGA.IO_L3N_T0L_N5_AD15N_65 | V8 | Bank 65 | I/O | User defined | |
| J1.59 | DGND | DGND | - | - | G | - | Digital ground |
| J1.61 | IO_L1P_T0L_N0_DBC_65 | FPGA.IO_L1P_T0L_N0_DBC_65 | W8 | Bank 65 | I/O | User defined | |
| J1.63 | IO_L1N_T0L_N1_DBC_65 | FPGA.IO_L1N_T0L_N1_DBC_65 | Y8 | Bank 65 | I/O | User defined | |
| J1.65 | DGND | DGND | - | - | G | - | Digital ground |
| J1.67 | VDDIO_BANK65 | S | |||||
| J1.69 | PS_MIO43_501 | CPU.PS_MIO43_501 | K19 | Bank 501 | I/O | 1.8V / 3.3V | (optional) MIO43 pin |
| J1.71 | PS_MIO45_501 | CPU.PS_MIO45_501 | K20 | Bank 501 | I/O | 1.8V / 3.3V | (optional) MIO45 pin |
| J1.73 | PS_MIO49_501 | CPU.PS_MIO45_501 | M18 | Bank 501 | I/O | 1.8V / 3.3V | |
| J1.75 | PS_MIO48_501 | CPU.PS_MIO44_501 | J21 | Bank 501 | I/O | 1.8V / 3.3V | |
| J1.77 | PS_MIO47_501 | CPU.PS_MIO43_501 | H21 | Bank 501 | I/O | 1.8V / 3.3V | |
| J1.79 | PS_MIO46_501 | CPU.PS_MIO42_501 | L20 | Bank 501 | I/O | 1.8V / 3.3V | |
| J1.81 | PS_MIO50_501 | CPU.PS_MIO41_501 | M19 | Bank 501 | I/O | 1.8V / 3.3V | |
| J1.83 | DGND | DGND | - | - | G | - | Digital ground |
| J1.85 | PS_MIO51_501 | CPU.PS_MIO51_501 | L21 | Bank 501 | I/O | 1.8V / 3.3V | |
| J1.87 | ETH_MDIO | CPU.PS_MIO77_502 | F20 | Bank 502 | I/O | 1.8V | 1kOhm pull-up |
| J1.89 | ETH_MDC | CPU.PS_MIO76_502 | B20 | Bank 502 | I/O | 1.8V | |
| J1.91 | ETH_LED1 | LAN.LED1 | 18 | - | 1.8V | ||
| J1.93 | ETH_LED2 | LAN.LED2 | 16 | - | 1.8V | ||
| J1.95 | DGND | DGND | - | - | G | - | Digital ground |
| J1.97 | ETH_TXRX1_N | LAN.TXRXM_B | 6 | D | |||
| J1.99 | ETH_TXRX1_N | LAN.TXRXP_B | 5 | D | |||
| J1.101 | DGND | DGND | - | - | G | - | Digital ground |
| J1.103 | ETH_TXRX0_N | LAN.ETH_TXRX0M_A | 3 | D | |||
| J1.105 | ETH_TXRX0_P | LAN.ETH_TXRX0P_A | 2 | D | |||
| J1.107 | PS_MIO28_501 | CPU.PS_MIO28_501 | K15 | Bank 501 | I/O | 1.8V / 3.3V | (optional) MIO28 pin |
| J1.109 | PS_MIO29_501 | CPU.PS_MIO28_501 | G16 | Bank 501 | I/O | 1.8V / 3.3V | (optional) MIO29 pin |
| J1.111 | USB_CPEN | USB.CPEN | 7 | 3.3V | |||
| J1.113 | USB_VBUS | USB.VBUS | 2 | ||||
| J1.115 | USB_ID | USB.ID | 1 | ||||
| J1.117 | DGND | DGND | - | - | G | - | Digital ground |
| J1.119 | PS_MODE0 | CPU.PS_MODE0 | CPU.P19 | Bank 503 | I/O | 1.8V or 3.3V | This signal is pulled up (100k) or down (10kOhm) resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[0]=0) |
| J1.119 | PS_MODE1 | CPU.PS_MODE1 | CPU.P20 | Bank 503 | I/O | 1.8V or 3.3V | This signal is pulled up (100k) or down (10kOhm) resistor to select proper bootstrap configuration. Default configuration: pull-up (BOOT_MODE[1]=1) |
| J1.119 | PS_MODE2 | CPU.PS_MODE2 | CPU.R20 | Bank 503 | I/O | 1.8V or 3.3V | This signal is pulled up (100k) or down (10kOhm) resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[2]=0) |
| J1.119 | PS_MODE3 | CPU.PS_MODE3 | CPU.T20 | Bank 503 | I/O | 1.8V or 3.3V | This signal is pulled up (100k) or down (10kOhm) resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[3]=0) |
| J1.127 | DGND | DGND | - | - | G | - | Digital ground |
| J1.129 | PS_MIO31_501 | CPU.PS_MIO31_501 | CPU.H16 | Bank 501 | I/O | 1.8V or 3.3V | |
| J1.131 | PS_MIO32_501 | CPU.PS_MIO32_501 | CPU.J16 | Bank 501 | I/O | 1.8V or 3.3V | |
| J1.133 | PS_MIO33_501 | CPU.PS_MIO33_501 | CPU.L16 | Bank 501 | I/O | 1.8V or 3.3V | |
| J1.135 | PS_MIO34_501 | CPU.PS_MIO34_501 | CPU.L17 | Bank 501 | I/O | 1.8V or 3.3V | |
| J1.137 | MEM_WPn | EEPROM.WP | 7 | 3.3V | |||
| J1.139 | DGND | DGND | - | - | G | - | Digital ground |
SOM J1 EVEN pins (2 to 140) declaration[edit | edit source]
| Pin | Pin Name | Internal Connections | Ball/pin # | Supply Group | Type | Voltage | Note |
| J1.2 | VDDIO_BANK65 | S | |||||
| J1.4 | DGND | DGND | - | - | - | G | Digital ground |
| J1.6 | IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 | FPGA.IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 | H9 | Bank 65 | I/O | User defined | |
| J1.8 | IO_L24N_T3U_N11_PERSTN0_65 | FPGA.IO_L24N_T3U_N11_PERSTN0_65 | H8 | Bank 65 | I/O | User defined | |
| J1.10 | IO_L22P_T3U_N6_DBC_AD0P_65 | FPGA.IO_L22P_T3U_N6_DBC_AD0P_65 | K8 | Bank 65 | I/O | User defined | |
| J1.12 | IO_L22N_T3U_N7_DBC_AD0N_65 | FPGA.IO_L22N_T3U_N7_DBC_AD0N_65 | K7 | Bank 65 | I/O | User defined | |
| J1.14 | DGND | DGND | - | - | - | G | Digital ground |
| J1.16 | IO_L20P_T3L_N2_AD1P_65 | FPGA.IO_L20P_T3L_N2_AD1P_65 | J6 | Bank 65 | I/O | User defined | |
| J1.18 | IO_L20N_T3L_N3_AD1N_65 | FPGA.IO_L20N_T3L_N3_AD1N_65 | H6 | Bank 65 | I/O | User defined | |
| J1.20 | IO_L18P_T2U_N10_AD2P_65 | FPGA.IO_L18P_T2U_N10_AD2P_65 | M8 | Bank 65 | I/O | User defined | |
| J1.22 | IO_L18N_T2U_N11_AD2N_65 | FPGA.IO_L18N_T2U_N11_AD2N_65 | L8 | Bank 65 | I/O | User defined | |
| J1.24 | DGND | DGND | - | - | - | G | Digital ground |
| J1.26 | IO_L16P_T2U_N6_QBC_AD3P_65 | FPGA.IO_L16P_T2U_N6_QBC_AD3P_65 | P7 | Bank 65 | I/O | User defined | |
| J1.28 | IO_L16N_T2U_N7_QBC_AD3N_65 | FPGA.IO_L16N_T2U_N7_QBC_AD3N_65 | P6 | Bank 65 | I/O | User defined | |
| J1.30 | DGND | DGND | - | - | - | G | Digital ground |
| J1.32 | IO_L14P_T2L_N2_GC_65 | FPGA.IO_L14P_T2L_N2_GC_65 | M6 | Bank 65 | I/O | User defined | |
| J1.34 | IO_L14N_T2L_N3_GC_65 | FPGA.IO_L14N_T2L_N3_GC_65 | L5 | Bank 65 | I/O | User defined | |
| J1.36 | IO_L12P_T1U_N10_GC_65 | FPGA.IO_L12P_T1U_N10_GC_65 | L3 | Bank 65 | I/O | User defined | |
| J1.38 | DGND | DGND | - | - | - | G | Digital ground |
| J1.40 | IO_L12N_T1U_N11_GC_65 | FPGA.IO_L12N_T1U_N11_GC_65 | L2 | Bank 65 | I/O | User defined | |
| J1.42 | IO_L10P_T1U_N6_QBC_AD4P_65 | FPGA.IO_L10P_T1U_N6_QBC_AD4P_65 | H4 | Bank 65 | I/O | User defined | |
| J1.44 | IO_L10N_T1U_N7_QBC_AD4N_65 | FPGA.IO_L10N_T1U_N7_QBC_AD4N_65 | H3 | Bank 65 | I/O | User defined | |
| J1.46 | IO_L8P_T1L_N2_AD5P_65 | FPGA.IO_L8P_T1L_N2_AD5P_65 | J1 | Bank 65 | I/O | User defined | |
| J1.48 | DGND | DGND | - | - | - | G | Digital ground |
| J1.50 | IO_L8N_T1L_N3_AD5N_65 | FPGA.IO_L8N_T1L_N3_AD5N_65 | H1 | Bank 65 | I/O | User defined | |
| J1.52 | IO_L6P_T0U_N10_AD6P_65 | FPGA.IO_L6P_T0U_N10_AD6P_65 | R6 | Bank 65 | I/O | User defined | |
| J1.54 | IO_L6N_T0U_N11_AD6N_65 | FPGA.IO_L6N_T0U_N11_AD6N_65 | T6 | Bank 65 | I/O | User defined | |
| J1.56 | IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 | FPGA.IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65 | R8 | Bank 65 | I/O | User defined | |
| J1.58 | IO_L4N_T0U_N7_DBC_AD7N_65 | FPGA.IO_L4N_T0U_N7_DBC_AD7N_65 | T8 | Bank 65 | I/O | User defined | |
| J1.60 | DGND | DGND | - | - | - | G | Digital ground |
| J1.62 | IO_L2P_T0L_N2_65 | FPGA.IO_L2P_T0L_N2_65 | U9 | Bank 65 | I/O | User defined | |
| J1.64 | IO_L2N_T0L_N3_65 | FPGA.IO_L2N_T0L_N3_65 | V9 | Bank 65 | I/O | User defined | |
| J1.66 | VDDIO_BANK65 | S | |||||
| J1.68 | VDDIO_BANK65 | S | |||||
| J1.70 | IO_T1U_N12_65 | FPGA.IO_T1U_N12_65 | H2 | Bank 65 | I/O | User defined | (optional) PL pin |
| J1.72 | IO_T2U_N12_65 | FPGA.IO_T2U_N12_65 | P9 | Bank 65 | I/O | User defined | (optional) PL pin |
| J1.74 | VREF_65 | FPGA.VREF_65 | R9 | Bank 65 | S | on-board 1kohm pull-down | |
| J1.76 | IO_T1U_N12_65 | FPGA.IO_T1U_N12_65 | K5 | Bank 65 | I/O | User defined | (optional) PL pin |
| J1.78 | PS_MIO23_500 | CPU.PS_MIO23_500 | AB18 | Bank 500 | I/O | 1.8V / 3.3V | |
| J1.80 | PS_MIO24_500 | CPU.PS_MIO23_500 | AB19 | Bank 500 | I/O | 1.8V / 3.3V | |
| J1.82 | PS_MIO25_500 | CPU.PS_MIO23_500 | AB21 | Bank 500 | I/O | 1.8V / 3.3V | |
| J1.84 | PS_MIO39_501 | CPU.PS_MIO39_501 | H19 | Bank 501 | I/O | 1.8V / 3.3V | |
| J1.86 | DGND | DGND | - | - | - | G | Digital ground |
| J1.88 | PS_MIO38_501 | CPU.PS_MIO38_501 | H18 | Bank 501 | I/O | 1.8V / 3.3V | |
| J1.90 | ETH_INTn | LAN.ETH_INTn | 9 | D | |||
| J1.92 | DGND | DGND | - | - | - | G | Digital ground |
| J1.94 | ETH_TXRX3_N | LAN.TXRXM_D | 11 | D | |||
| J1.96 | ETH_TXRX3_P | LAN.TXRXP_D | 10 | D | |||
| J1.98 | DGND | DGND | - | - | - | G | Digital ground |
| J1.100 | ETH_TXRX2_N | LAN.TXRXM_C | 8 | D | |||
| J1.102 | ETH_TXRX2_P | LAN.TXRXP_C | 7 | D | |||
| J1.104 | DGND | DGND | - | - | - | G | Digital ground |
| J1.106 | RFU | - | - | - | - | - | Reserved for future use. Must be left floating. |
| J1.108 | PS_MGTRTXP1_505 | CPU.PS_MGTRTXP1_505 | D23 | Bank 505 | I/O | ||
| J1.110 | PS_MGTRTXN1_505 | CPU.PS_MGTRTXN1_505 | D24 | Bank 505 | I/O | ||
| J1.112 | DGND | DGND | - | - | - | G | Digital ground |
| J1.114 | USB_D_P | USB.DP | 6 | D | |||
| J1.116 | USB_D_N | USB.DM | 5 | D | |||
| J1.118 | DGND | DGND | - | - | - | G | Digital ground |
| J1.120 | PS_MGTRRXP1_505 | CPU.PS_MGTRRXP1_505 | D27 | Bank 505 | I/O | ||
| J1.122 | PS_MGTRRXN1_505 | CPU.PS_MGTRRXN1_505 | D28 | Bank 505 | I/O | ||
| J1.124 | PS_MIO30_501 | CPU.PS_MIO30_501 | F16 | Bank 501 | I/O | 1.8V / 3.3V | (optional) MIO30 pin |
| J1.126 | PS_MGTREFCLK0P_505 | CPU.PS_MGTREFCLK0P_505 | F23 | Bank 505 | I/O | ||
| J1.128 | PS_MGTREFCLK0N_505 | CPU.PS_MGTREFCLK0N_505 | F24 | Bank 505 | I/O | ||
| J1.130 | DGND | DGND | - | - | - | G | Digital ground |
| J1.132 | PS_MGTRTXP0_505 | CPU.PS_MGTRTXP0_505 | E25 | Bank 505 | I/O | ||
| J1.134 | PS_MGTRTXN0_505 | CPU.PS_MGTRTXN0_505 | E26 | Bank 505 | I/O | ||
| J1.136 | PS_MGTRRXP0_505 | CPU.PS_MGTRRXP0_505 | F27 | Bank 505 | I/O | ||
| J1.138 | PS_MGTRRXN0_505 | CPU.PS_MGTRRXN0_505 | F28 | Bank 505 | I/O | ||
| J1.140 | DGND | DGND | - | - | - | G | Digital ground |
SOM J2 ODD pins (1 to 139) declaration[edit | edit source]
| Pin | Pin Name | Internal Connections | Ball/pin # | Supply Group | Type | Voltage | Note |
| J2.1 | DGND | DGND | - | - | G | - | Digital ground |
| J2.3 | DGND | DGND | - | - | G | - | Digital ground |
| J2.5 | IO_L8P_T1L_N2_AD5P_66 | FPGA.IO_L8P_T1L_N2_AD5P_66 | A2 | Bank 66 | I/O | User defined | |
| J2.7 | IO_L8N_T1L_N3_AD5N_66 | FPGA.IO_L8N_T1L_N3_AD5N_66 | A1 | Bank 66 | I/O | User defined | |
| J2.9 | IO_L6P_T0U_N10_AD6P_66 | FPGA.IO_L6P_T0U_N10_AD6P_66 | G5 | Bank 66 | I/O | User defined | |
| J2.11 | IO_L6N_T0U_N11_AD6N_66 | FPGA.IO_L6N_T0U_N11_AD6N_66 | F5 | Bank 66 | I/O | User defined | |
| J2.13 | DGND | DGND | - | - | G | - | Digital ground |
| J2.15 | IO_L3P_T0L_N4_AD15P_66 | FPGA.IO_L3P_T0L_N4_AD15P_66 | F2 | Bank 66 | I/O | User defined | |
| J2.17 | IO_L3N_T0L_N5_AD15N_66 | FPGA.IO_L3N_T0L_N5_AD15N_66 | E2 | Bank 66 | I/O | User defined | |
| J2.19 | IO_L2P_T0L_N2_66 | FPGA.IO_L2P_T0L_N2_66 | E1 | Bank 66 | I/O | User defined | |
| J2.21 | IO_L2N_T0L_N3_66 | FPGA.IO_L2N_T0L_N3_66 | D1 | Bank 66 | I/O | User defined | |
| J2.23 | DGND | DGND | - | - | G | - | Digital ground |
| J2.25 | IO_L22P_T3U_N6_DBC_AD0P_66 | FPGA.IO_L22P_T3U_N6_DBC_AD0P_66 | C8 | Bank 66 | I/O | User defined | |
| J2.27 | IO_L22N_T3U_N7_DBC_AD0N_66 | FPGA.IO_L22N_T3U_N7_DBC_AD0N_66 | B8 | Bank 66 | I/O | User defined | |
| J2.29 | IO_L21P_T3L_N4_AD8P_66 | FPGA.IO_L21P_T3L_N4_AD8P_66 | A7 | Bank 66 | I/O | User defined | |
| J2.31 | IO_L21N_T3L_N5_AD8N_66 | FPGA.IO_L21N_T3L_N5_AD8N_66 | A6 | Bank 66 | I/O | User defined | |
| J2.33 | DGND | DGND | - | - | G | - | Digital ground |
| J2.35 | IO_L19P_T3L_N0_DBC_AD9P_66 | FPGA.IO_L19P_T3L_N0_DBC_AD9P_66 | B5 | Bank 66 | I/O | User defined | |
| J2.37 | IO_L19N_T3L_N1_DBC_AD9N_66 | FPGA.IO_L19N_T3L_N1_DBC_AD9N_66 | A5 | Bank 66 | I/O | User defined | |
| J2.39 | IO_L18P_T2U_N10_AD2P_66 | FPGA.IO_L18P_T2U_N10_AD2P_66 | E9 | Bank 66 | I/O | User defined | |
| J2.41 | IO_L18N_T2U_N11_AD2N_66 | FPGA.IO_L18N_T2U_N11_AD2N_66 | D9 | Bank 66 | I/O | User defined | |
| J2.43 | DGND | DGND | - | - | G | - | Digital ground |
| J2.45 | IO_L15P_T2L_N4_AD11P_66 | FPGA.IO_L15P_T2L_N4_AD11P_66 | G6 | Bank 66 | I/O | User defined | |
| J2.47 | IO_L15N_T2L_N5_AD11N_66 | FPGA.IO_L15N_T2L_N5_AD11N_66 | F6 | Bank 66 | I/O | User defined | |
| J2.49 | DGND | DGND | - | - | G | - | Digital ground |
| J2.51 | IO_L13P_T2L_N0_GC_QBC_66 | FPGA.IO_L13P_T2L_N0_GC_QBC_66 | D7 | Bank 66 | I/O | User defined | |
| J2.53 | IO_L13N_T2L_N1_GC_QBC_66 | FPGA.IO_L13N_T2L_N1_GC_QBC_66 | D6 | Bank 66 | I/O | User defined | |
| J2.55 | DGND | DGND | - | - | G | - | Digital ground |
| J2.57 | IO_L11P_T1U_N8_GC_66 | FPGA.IO_L11P_T1U_N8_GC_66 | D4 | Bank 66 | I/O | User defined | |
| J2.59 | IO_L11N_T1U_N9_GC_66 | FPGA.IO_L11N_T1U_N9_GC_66 | C4 | Bank 66 | I/O | User defined | |
| J2.61 | DGND | DGND | - | - | G | - | Digital ground |
| J2.63 | IO_L10P_T1U_N6_QBC_AD4P_66 | FPGA.IO_L10P_T1U_N6_QBC_AD4P_66 | B4 | Bank 66 | I/O | User defined | |
| J2.65 | IO_L10N_T1U_N7_QBC_AD4N_66 | FPGA.IO_L10N_T1U_N7_QBC_AD4N_66 | A4 | Bank 66 | I/O | User defined | |
| J2.67 | IO_T1U_N12_66 | FPGA.IO_T1U_N12_66 | D2 | Bank 66 | I/O | User defined | |
| J2.69 | IO_T0U_N12_VRP_66 | FPGA.IO_T0U_N12_VRP_66 | G4 | Bank 66 | I/O | User defined | |
| J2.71 | DGND | DGND | - | - | G | - | Digital ground |
| J2.73 | IO_T3U_N12_66 | FPGA.IO_T3U_N12_66 | C7 | Bank 66 | I/O | User defined | |
| J2.75 | IO_T2U_N12_66 | FPGA.IO_T2U_N12_66 | E7 | Bank 66 | I/O | User defined | |
| J2.77 | RFU | - | - | - | - | - | Reserved for future use. Must be left floating. |
| J2.79 | RFU | - | - | - | - | - | Reserved for future use. Must be left floating. |
| J2.81 | RFU | - | - | - | - | - | Reserved for future use. Must be left floating. |
| J2.83 | ETH_RSTn | LAN.RESET_N | 43 | I | 1.8V | Internally connected to ETH_VDDIO via 10K resistor and to SOM_PER_RSTn | |
| J2.85 | USB_RSTn | USB.RESETB | 22 | I | 1.8V | Internally connected to USB_VDDIO via 10K resistor | |
| J2.87 | CAN_STBYn | CAN.STB | 8 | I | Internally connected to VDDIO_BANK501 via 10K resistor | ||
| J2.89 | PS_MIO27_501 | CPU.PS_MIO27_501 | F16 | Bank 501 | I/O | 1.8V / 3.3V | (optional) MIO27 pin |
| J2.91 | PS_MIO35_501 | CPU.PS_MIO35_501 | F16 | Bank 501 | I/O | 1.8V / 3.3V | (optional) MIO35 pin |
| J2.93 | RTC_32KHZ | RTC.32KHZ | 1 | 3.3V | O | 3.3V | |
| J2.95 | RTC_RSTn | RTC.RSTn | 4 | 3.3V | I/O | 3.3V | |
| J2.97 | ADC_N | FPGA.VN | T12 | Bank 503 | A | ||
| J2.99 | ADC_P | FPGA.VP | R13 | Bank 503 | A | ||
| J2.101 | AGND | AGND | - | - | G | - | Analog ground |
| J2.103 | SOM_PER_RSTn | - | - | - | - | - | Peripheral reset buffer (NOR, eMMC, LAN PHY, USB PHY) |
| J2.105 | CAN_L | CAN.CANL | 6 | - | D | - | |
| J2.107 | CAN_H | CAN.CANH | 7 | - | D | - | |
| J2.109 | DGND | DGND | - | - | G | - | Digital ground |
| J2.111 | RTC_INTn/SQW | RTC.INT/SQW | 3 | 3.3V | I/O | 3.3V | It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet. |
| J2.113 | RTC_VBAT | RTC.VBAT | 6 | - | S | - | |
| J2.115 | VBAT | CPU.VCC_PSBATT | Y18 | - | S | - | |
| J2.117 | DGND | DGND | - | - | G | - | Digital ground |
| J2.119 | 3.3VIN | 3.3VIN | - | 3.3VIN | S | Auxiliary 3.3V Power Supply | |
| J2.121 | 3.3VIN | 3.3VIN | - | 3.3VIN | S | Auxiliary 3.3V Power Supply | |
| J2.123 | 3.3VIN | 3.3VIN | - | 3.3VIN | S | Auxiliary 3.3V Power Supply | |
| J2.125 | DGND | DGND | - | - | G | - | Digital ground |
| J2.127 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.129 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.131 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.133 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.135 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.137 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.139 | DGND | DGND | - | - | G | - | Digital ground |
SOM J2 EVEN pins (2 to 140) declaration[edit | edit source]
| Pin | Pin Name | Internal Connections | Ball/pin # | Supply Group | Type | Voltage | Note |
| J2.2 | DGND | DGND | - | - | G | - | Digital ground |
| J2.4 | IO_L9P_T1L_N4_AD12P_66 | FPGA.IO_L9P_T1L_N4_AD12P_66 | B3 | Bank 66 | I/O | User defined | |
| J2.6 | IO_L9N_T1L_N5_AD12N_66 | FPGA.IO_L9N_T1L_N5_AD12N_66 | A3 | Bank 66 | I/O | User defined | |
| J2.8 | IO_L7P_T1L_N0_QBC_AD13P_66 | FPGA.IO_L7P_T1L_N0_QBC_AD13P_66 | C1 | Bank 66 | I/O | User defined | |
| J2.10 | IO_L7N_T1L_N1_QBC_AD13N_66 | FPGA.IO_L7N_T1L_N1_QBC_AD13N_66 | B1 | Bank 66 | I/O | User defined | |
| J2.12 | DGND | DGND | - | - | G | - | Digital ground |
| J2.14 | IO_L5P_T0U_N8_AD14P_66 | FPGA.IO_L5P_T0U_N8_AD14P_66 | E4 | Bank 66 | I/O | User defined | |
| J2.16 | IO_L5N_T0U_N9_AD14N_66 | FPGA.IO_L5N_T0U_N9_AD14N_66 | E3 | Bank 66 | I/O | User defined | |
| J2.18 | IO_L4P_T0U_N6_DBC_AD7P_66 | FPGA.IO_L4P_T0U_N6_DBC_AD7P_66 | G3 | Bank 66 | I/O | User defined | |
| J2.20 | IO_L4N_T0U_N7_DBC_AD7N_66 | FPGA.IO_L4N_T0U_N7_DBC_AD7N_66 | F3 | Bank 66 | I/O | User defined | |
| J2.22 | DGND | DGND | - | - | G | - | Digital ground |
| J2.24 | IO_L24P_T3U_N10_66 | FPGA.IO_L24P_T3U_N10_66 | C9 | Bank 66 | I/O | User defined | |
| J2.26 | IO_L24N_T3U_N11_66 | FPGA.IO_L24N_T3U_N11_66 | B9 | Bank 66 | I/O | User defined | |
| J2.28 | IO_L23P_T3U_N8_66 | FPGA.IO_L23P_T3U_N8_66 | A9 | Bank 66 | I/O | User defined | |
| J2.30 | IO_L23N_T3U_N9_66 | FPGA.IO_L23N_T3U_N9_66 | A8 | Bank 66 | I/O | User defined | |
| J2.32 | DGND | DGND | - | - | G | - | Digital ground |
| J2.34 | IO_L20P_T3L_N2_AD1P_66 | FPGA.IO_L20P_T3L_N2_AD1P_66 | C6 | Bank 66 | I/O | User defined | |
| J2.36 | IO_L20N_T3L_N3_AD1N_66 | FPGA.IO_L20N_T3L_N3_AD1N_66 | B6 | Bank 66 | I/O | User defined | |
| J2.38 | IO_L1P_T0L_N0_DBC_66 | FPGA.IO_L1P_T0L_N0_DBC_66 | G1 | Bank 66 | I/O | User defined | |
| J2.40 | IO_L1N_T0L_N1_DBC_66 | FPGA.IO_L1N_T0L_N1_DBC_66 | F1 | Bank 66 | I/O | User defined | |
| J2.42 | DGND | DGND | - | - | G | - | Digital ground |
| J2.44 | IO_L17P_T2U_N8_AD10P_66 | FPGA.IO_L17P_T2U_N8_AD10P_66 | F8 | Bank 66 | I/O | User defined | |
| J2.46 | IO_L17N_T2U_N9_AD10N_66 | FPGA.IO_L17N_T2U_N9_AD10N_66 | E8 | Bank 66 | I/O | User defined | |
| J2.48 | IO_L16P_T2U_N6_QBC_AD3P_66 | FPGA.IO_L16P_T2U_N6_QBC_AD3P_66 | G8 | Bank 66 | I/O | User defined | |
| J2.50 | IO_L16N_T2U_N7_QBC_AD3N_66 | FPGA.IO_L16N_T2U_N7_QBC_AD3N_66 | F7 | Bank 66 | I/O | User defined | |
| J2.52 | DGND | DGND | - | - | G | - | Digital ground |
| J2.54 | IO_L14P_T2L_N2_GC_66 | FPGA.IO_L14P_T2L_N2_GC_66 | E5 | Bank 66 | I/O | User defined | |
| J2.56 | IO_L14N_T2L_N3_GC_66 | FPGA.IO_L14N_T2L_N3_GC_66 | D5 | Bank 66 | I/O | User defined | |
| J2.58 | DGND | DGND | - | - | G | - | Digital ground |
| J2.60 | IO_L12P_T1U_N10_GC_66 | FPGA.IO_L12P_T1U_N10_GC_66 | C3 | Bank 66 | I/O | User defined | |
| J2.62 | IO_L12N_T1U_N11_GC_66 | FPGA.IO_L12N_T1U_N11_GC_66 | C2 | Bank 66 | I/O | User defined | |
| J2.64 | DGND | DGND | - | - | G | - | Digital ground |
| J2.66 | VDDIO_BANK66 | FPGA.VCCO_66 | B7 D3 E6 |
Bank 66 | S | User defined | Bank66 I/O Power Supply |
| J2.68 | VDDIO_BANK66 | FPGA.VCCO_66 | B7 D3 E6 |
Bank 66 | S | User defined | Bank66 I/O Power Supply |
| J2.70 | VDDIO_BANK66 | FPGA.VCCO_66 | B7 D3 E6 |
Bank 66 | S | User defined | Bank66 I/O Power Supply |
| J2.72 | VDDIO_BANK66 | FPGA.VCCO_66 | B7 D3 E6 |
Bank 66 | S | User defined | Bank66 I/O Power Supply |
| J2.74 | VREF_66 | FPGA.VREF_66 | G9 | Bank 66 | S | on-board 1kohm pull-down | |
| J2.76 | PS_ERROR_OUT | CPU.PS_ERROR_OUT | CPU.P17 | Bank 503 | I/O | 1.8V or 3.3V | This signal has an optional internal pull-up (10k) |
| J2.78 | PS_ERROR_STATUS | CPU.PS_ERROR_STATUS | CPU.M20 | Bank 503 | I/O | 1.8V or 3.3V | This signal has an internal pull-up (10k) |
| J2.80 | JTAG_TDO | CPU.PS_JTAG_TDO | T21 | Bank 503 | O | 1.8V or 3.3V | |
| J2.82 | JTAG_TDI | CPU.PS_JTAG_TDI | R18 | Bank 503 | I | 1.8V or 3.3V | |
| J2.84 | JTAG_TMS | CPU.PS_JTAG_TMS | N21 | Bank 503 | I | 1.8V or 3.3V | |
| J2.86 | JTAG_TCK | CPU.PS_JTAG_TCK | R19 | Bank 503 | I | 1.8V or 3.3V | |
| J2.88 | DGND | DGND | - | - | G | - | Digital ground |
| J2.90 | PS_INIT_B | FPGA.PS_INIT_B | P21 | Bank 503 | I/O | 1.8V or 3.3V | For further details, please refer to PL initialization signals |
| J2.92 | PS_PROG_B | FPGA.PS_PROG_B | V10 | Bank 503 | I | 1.8V or 3.3V | For further details, please refer to PL initialization signals
(10 kohm pull-up resistor is already mounted on ONDA SOM) |
| J2.94 | PS_DONE | FPGA.PS_DONE | M21 | Bank 503 | I/O | 1.8V or 3.3V | For further details, please refer to PL initialization signals
(10 kohm pull-up resistor is already mounted on ONDA SOM) |
| J2.96 | WD_SET2 | WDT.SET2 | 6 | 3.3V | I | 3.3V | |
| J2.98 | WD_SET1 | WDT.SET1 | 5 | 3.3V | I | 3.3V | |
| J2.100 | WD_SET0 | WDT.SET0 | 4 | 3.3V | I | 3.3V | |
| J2.102 | DGND | DGND | - | - | G | - | Digital ground |
| J2.104 | PS_MIO36_501 | CPU.PS_MIO36_501 | K17 | Bank 501 | I/O | 1.8V or 3.3V | For further details, please refer to Resetscheme#PS_MIO50_501 |
| J2.106 | PS_MIO37_501 | CPU.PS_MIO37_501 | J17 | Bank 501 | I/O | 1.8V or 3.3V | For further details, please refer to Reset scheme#PS_MIO51_501 |
| J2.108 | SOM_PGOOD | n.a. | 3.3V | O | 3.3V | Internally connected to +VIN_3V3 via 10K resistor | |
| J2.110 | CB_PGOOD | n.a. | 3.3VIN | I | 3.3V | Internally connected to +VIN_3V3 via 10K resistor | |
| J2.112 | PS_SRST_B | CPU.PS_SRST_B | N19 | Bank 503 | I | 1.8V or 3.3V | Internally connected to Bank 503 power supply via 10K resistor |
| J2.114 | PS_POR_B | CPU.PS_POR_B WD.WDOn |
P16 7 |
Bank 503 | I/O | 1.8V or 3.3V | For further details, please refer to Reset_scheme#PORSTn |
| J2.116 | MRSTn | Voltage monitor | 3.3VIN | I | 3.3V | For further details, please refer to Reset scheme | |
| J2.118 | DGND | DGND | - | - | G | - | Digital ground |
| J2.120 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.122 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.124 | DGND | DGND | - | - | G | - | Digital ground |
| J2.126 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.128 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.130 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.132 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.134 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.136 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.138 | VIN | VIN | - | VIN | S | SOM Power Supply | |
| J2.140 | DGND | DGND | - | - | G | - | Digital ground |
SOM J3 ODD pins (1 to 139)declaration[edit | edit source]
| Pin | Pin Name | Internal Connections | Ball/pin # | Supply Group | Type | Voltage | Note |
| J3.1 | DGND | DGND | - | - | G | - | Digital ground |
| J3.3 | MGTREFCLK0N | FPGA.MGTREFCLK0N_224 | Y5 | MGTAVCC | D | ||
| J3.5 | MGTREFCLK0P | FPGA.MGTREFCLK0P_224 | Y6 | MGTAVCC | D | ||
| J3.7 | DGND | DGND | - | - | G | - | Digital ground |
| J3.9 | MGTHTXP0 | FPGA.MGTHTXP0_224 | W4 | MGTAVCC | D | ||
| J3.11 | MGTHTXN0 | FPGA.MGTHTXN0_224 | W3 | MGTAVCC | D | ||
| J3.13 | DGND | DGND | - | - | G | - | Digital ground |
| J3.15 | MGTHTXP1 | FPGA.MGTHTXP1_224 | U4 | MGTAVCC | D | ||
| J3.17 | MGTHTXN1 | FPGA.MGTHTXN1_224 | U3 | MGTAVCC | D | ||
| J3.19 | DGND | DGND | - | - | G | - | Digital ground |
| J3.21 | MGTHTXP2 | FPGA.MGTHTXP2_224 | R4 | MGTAVCC | D | ||
| J3.23 | MGTHTXN2 | FPGA.MGTHTXN2_224 | R3 | MGTAVCC | D | ||
| J3.25 | DGND | DGND | - | - | G | - | Digital ground |
| J3.27 | MGTHTXP3 | FPGA.MGTHTXP3_224 | N4 | MGTAVCC | D | ||
| J3.29 | MGTHTXN3 | FPGA.MGTHTXN3_224 | N3 | MGTAVCC | D | ||
| J3.31 | DGND | DGND | - | - | G | - | Digital ground |
| J3.33 | PG_0V9_GTH | - | - | 3.3VIN | O | - | Power Good for 0V9 GTH power supply LDO regulator |
| J3.35 | EN_0V9_GTH | - | - | 3.3VIN | I | - | Power Enable for 0V9 GTH power supply LDO regulator |
| J3.37 | DGND | DGND | - | - | G | - | Digital ground |
| J3.39 | IO_L8P_HDGC_AD4P_43 | FPGA.IO_L8P_HDGC_AD4P_43 | AB11 | Bank 43 | I/O | User defined | |
| J3.41 | IO_L8N_HDGC_AD4N_43 | FPGA.IO_L8N_HDGC_AD4N_43 | AC11 | Bank 43 | I/O | User defined | |
| J3.43 | DGND | DGND | - | - | G | - | Digital ground |
| J3.45 | IO_L7P_HDGC_AD5P_43 | FPGA.IO_L7P_HDGC_AD5P_43 | AD11 | Bank 43 | I/O | User defined | |
| J3.47 | IO_L7N_HDGC_AD5N_43 | FPGA.IO_L7N_HDGC_AD5N_43 | AD10 | Bank 43 | I/O | User defined | |
| J3.49 | DGND | DGND | - | - | G | - | Digital ground |
| J3.51 | IO_L6P_HDGC_AD6P_43 | FPGA.IO_L6P_HDGC_AD6P_43 | AC12 | Bank 43 | I/O | User defined | |
| J3.53 | IO_L6N_HDGC_AD6N_43 | FPGA.IO_L6N_HDGC_AD6N_43 | AD12 | Bank 43 | I/O | User defined | |
| J3.55 | DGND | DGND | - | - | G | - | Digital ground |
| J3.57 | IO_L5P_HDGC_AD7P_43 | FPGA.IO_L5P_HDGC_AD7P_43 | AE12 | Bank 43 | I/O | User defined | |
| J3.59 | IO_L5N_HDGC_AD7N_43 | FPGA.IO_L5N_HDGC_AD7N_43 | AF12 | Bank 43 | I/O | User defined | |
| J3.61 | DGND | DGND | - | - | G | - | Digital ground |
| J3.63 | IO_L4P_AD8P_43 | FPGA.IO_L4P_AD8P_43 | AE10 | Bank 43 | I/O | User defined | |
| J3.65 | IO_L4N_AD8N_43 | FPGA.IO_L4N_AD8N_43 | AF10 | Bank 43 | I/O | User defined | |
| J3.67 | DGND | DGND | - | - | G | - | Digital ground |
| J3.69 | DGND | DGND | - | - | G | - | Digital ground |
| J3.71 | IO_L3P_AD9P_43 | FPGA.IO_L3P_AD9P_43 | AH12 | Bank 43 | I/O | User defined | |
| J3.73 | IO_L3N_AD9N_43 | FPGA.IO_L3N_AD9N_43 | AH11 | Bank 43 | I/O | User defined | |
| J3.75 | DGND | DGND | - | - | G | - | Digital ground |
| J3.77 | IO_L2P_AD10P_43 | FPGA.IO_L2P_AD10P_43 | AF11 | Bank 43 | I/O | User defined | |
| J3.79 | IO_L2N_AD10N_43 | FPGA.IO_L2N_AD10N_43 | AG11 | Bank 43 | I/O | User defined | |
| J3.81 | DGND | DGND | - | - | G | - | Digital ground |
| J3.83 | IO_L1P_AD11P_43 | FPGA.IO_L1P_AD11P_43 | AG10 | Bank 43 | I/O | User defined | |
| J3.85 | IO_L1N_AD11N_43 | FPGA.IO_L1N_AD11N_43 | AH10 | Bank 43 | I/O | User defined | |
| J3.87 | DGND | DGND | - | - | G | - | Digital ground |
| J3.89 | RFU | - | - | - | - | - | Reserved for future use. Must be left floating. |
| J3.91 | RFU | - | - | - | - | - | Reserved for future use. Must be left floating. |
| J3.93 | DGND | DGND | - | - | G | - | Digital ground |
| J3.95 | VDDIO_BANK43-44 | FPGA.VCCO_13 | AC10 AG12 AA14 AD13 |
Bank 43-44 | S | User defined | Bank43-44 I/O Power Supply |
| J3.97 | VDDIO_BANK43-44 | FPGA.VCCO_13 | AC10 AG12 AA14 AD13 |
Bank 43-44 | S | User defined | Bank43-44 I/O Power Supply |
| J3.99 | VDDIO_BANK43-44 | FPGA.VCCO_13 | AC10 AG12 AA14 AD13 |
Bank 43-44 | S | User defined | Bank43-44 I/O Power Supply |
| J3.101 | DGND | DGND | - | - | G | - | Digital ground |
| J3.103 | DGND | DGND | - | - | G | - | Digital ground |
| J3.105 | IO_L11P_AD9P_44 | FPGA.IO_L11P_AD9P_44 | W12 | Bank 44 | I/O | User defined | |
| J3.107 | IO_L11N_AD9N_44 | FPGA.IO_L11N_AD9N_44 | W11 | Bank 44 | I/O | User defined | |
| J3.109 | DGND | DGND | - | - | G | - | Digital ground |
| J3.111 | IO_L9P_AD11P_44 | FPGA.IO_L9P_AD11P_44 | W14 | Bank 44 | I/O | User defined | |
| J3.113 | IO_L9N_AD11N_44 | FPGA.IO_L9N_AD11N_44 | W13 | Bank 44 | I/O | User defined | |
| J3.115 | DGND | DGND | - | - | G | - | Digital ground |
| J3.117 | IO_L7P_HDGC_44 | FPGA.IO_L7P_HDGC_44 | AA13 | Bank 44 | I/O | User defined | |
| J3.119 | IO_L7N_HDGC_44 | FPGA.IO_L7N_HDGC_44 | AB13 | Bank 44 | I/O | User defined | |
| J3.121 | DGND | DGND | - | - | G | - | Digital ground |
| J3.123 | IO_L5P_HDGC_44 | FPGA.IO_L5P_HDGC_44 | AD15 | Bank 44 | I/O | User defined | |
| J3.125 | IO_L5N_HDGC_44 | FPGA.IO_L5N_HDGC_44 | AD14 | Bank 44 | I/O | User defined | |
| J3.127 | DGND | DGND | - | - | G | - | Digital ground |
| J3.129 | IO_L3P_AD13P_44 | FPGA.IO_L3P_AD13P_44 | AG13 | Bank 44 | I/O | User defined | |
| J3.131 | IO_L3N_AD13N_44 | FPGA.IO_L3N_AD13N_44 | AH13 | Bank 44 | I/O | User defined | |
| J3.133 | DGND | DGND | - | - | G | - | Digital ground |
| J3.135 | IO_L1P_AD15P_44 | FPGA.IO_L1P_AD15P_44 | AE15 | Bank 44 | I/O | User defined | |
| J3.137 | IO_L1N_AD15N_44 | FPGA.IO_L1N_AD15N_44 | AE14 | Bank 44 | I/O | User defined | |
| J3.139 | DGND | DGND | - | - | G | - | Digital ground |
SOM J3 EVEN pins (2 to 140) declaration[edit | edit source]
| Pin | Pin Name | Internal Connections | Ball/pin # | Supply Group | Type | Voltage | Note |
| J3.2 | DGND | DGND | - | - | G | - | Digital ground |
| J3.4 | DGND | DGND | - | - | G | - | Digital ground |
| J3.6 | MGTREFCLK1N | FPGA.MGTREFCLK1N_224 | V5 | MGTAVCC | D | ||
| J3.8 | MGTREFCLK1P | FPGA.MGTREFCLK1P_224 | V6 | MGTAVCC | D | ||
| J3.10 | DGND | DGND | - | - | G | - | Digital ground |
| J3.12 | MGTHRXP0 | FPGA.MGTHRXP0_224 | Y2 | MGTAVCC | D | ||
| J3.14 | MGTHRXN0 | FPGA.MGTHRXN0_224 | Y1 | MGTAVCC | D | ||
| J3.16 | DGND | DGND | - | - | G | - | Digital ground |
| J3.18 | MGTHRXP1 | FPGA.MGTHRXP1_224 | V2 | MGTAVCC | D | ||
| J3.20 | MGTHRXN1 | FPGA.MGTHRXN1_224 | V1 | MGTAVCC | D | ||
| J3.22 | DGND | DGND | - | - | G | - | Digital ground |
| J3.24 | MGTHRXP2 | FPGA.MGTHRXP2_224 | T2 | MGTAVCC | D | ||
| J3.26 | MGTHRXN2 | FPGA.MGTHRXN2_224 | T1 | MGTAVCC | D | ||
| J3.28 | DGND | DGND | - | - | G | - | Digital ground |
| J3.30 | MGTHRXP3 | FPGA.MGTHRXP3_224 | P2 | MGTAVCC | D | ||
| J3.32 | MGTHRXN3 | FPGA.MGTHRXN3_224 | P1 | MGTAVCC | D | ||
| J3.34 | DGND | DGND | - | - | G | - | Digital ground |
| J3.36 | DGND | DGND | - | - | G | - | Digital ground |
| J3.38 | IO_L12P_AD0P_43 | FPGA.IO_L12P_AD0P_43 | AB10 | Bank 43 | I/O | User defined | |
| J3.40 | IO_L12N_AD0N_43 | FPGA.IO_L12N_AD0N_43 | AB9 | Bank 43 | I/O | User defined | |
| J3.42 | DGND | DGND | - | - | G | - | Digital ground |
| J3.44 | IO_L11P_AD1P_43 | FPGA.IO_L11P_AD1P_43 | Y9 | Bank 43 | I/O | User defined | |
| J3.46 | IO_L11N_AD1N_43 | FPGA.IO_L11N_AD1N_43 | AA8 | Bank 43 | I/O | User defined | |
| J3.48 | DGND | DGND | - | - | G | - | Digital ground |
| J3.50 | IO_L10P_AD2P_43 | FPGA.IO_L10P_AD2P_43 | W10 | Bank 43 | I/O | User defined | |
| J3.52 | IO_L10N_AD2N_43 | FPGA.IO_L10N_AD2N_43 | Y10 | Bank 43 | I/O | User defined | |
| J3.54 | DGND | DGND | - | - | G | - | Digital ground |
| J3.56 | IO_L9P_AD3P_43 | FPGA.IO_L9P_AD3P_43 | AA11 | Bank 43 | I/O | User defined | |
| J3.58 | IO_L9N_AD3N_43 | FPGA.IO_L9N_AD3N_43 | AA10 | Bank 43 | I/O | User defined | |
| J3.60 | DGND | DGND | - | - | G | - | Digital ground |
| J3.62 | PG_0V9_VCU | - | - | 3.3VIN | O | - | Power Good for 0V9 VCU power supply LDO regulator |
| J3.64 | EN_0V9_VCU | - | - | 3.3VIN | I | - | Power Enable for 0V9 VCU power supply LDO regulator |
| J3.62 | PG_1V8_IO | - | - | 3.3VIN | O | - | Power Good for 1V8 I/O power supply regulator |
| J3.68 | DGND | DGND | - | - | G | - | Digital ground |
| J3.64 | EN_1V8_IO | - | - | 3.3VIN | I | - | Power Enable for 1V8 I/O power supply regulator |
| J3.72 | PG_0V85_MGT | - | - | 3.3VIN | O | - | Power Good for 0V85 GTR power supply LDO regulator |
| J3.74 | EN_0V85_MGT | - | - | 3.3VIN | I | - | Power Enable for 0V85 GTR power supply LDO regulator |
| J3.76 | PG_1V2_DDR | - | - | 3.3VIN | O | - | Power Good for 1V2 DDR power supply regulator |
| J3.78 | EN_1V2_DDR | - | - | 3.3VIN | I | - | Power Enable for 1V2 DDR power supply regulator |
| J3.80 | PG_2V5_PP | - | - | 3.3VIN | O | - | Power Good for 2V5 power supply regulator |
| J3.82 | EN_2V5_PP | - | - | 3.3VIN | I | - | Power Enable for 2V5 power supply regulator |
| J3.84 | PG_1V2_GTH | - | - | 3.3VIN | O | - | Power Good for 1V2 GTH power supply regulator |
| J3.86 | EN_1V2_GTH | - | - | VIN | I | - | Power Enable for 1V2 GTH power supply regulator |
| J3.88 | PG_1V8_AUX | - | - | 3.3VIN | O | - | Power Good for 1V8 AUX power supply regulator |
| J3.90 | EN_1V8_AUX | - | - | 3.3VIN | I | - | Power Enable for 1V8 AUX power supply regulator |
| J3.92 | PG_0V85_INT | - | - | 3.3VIN | O | - | Power Good for 0V85 power supply regulator |
| J3.94 | DGND | DGND | - | - | G | - | Digital ground |
| J3.96 | VDDIO_BANK43-44 | FPGA.VCCO_13 | AC10 AG12 AA14 AD13 |
Bank 43-44 | S | User defined | Bank43-44 I/O Power Supply |
| J3.98 | VDDIO_BANK43-44 | FPGA.VCCO_13 | AC10 AG12 AA14 AD13 |
Bank 43-44 | S | User defined | Bank43-44 I/O Power Supply |
| J3.100 | WDT_REARM | WD.WDI | 1 | 3.3VIN | I | - | Watchdog rearm pin |
| J3.102 | DGND | DGND | - | - | G | - | Digital ground |
| J3.104 | IO_L12P_AD8P_44 | FPGA.IO_L12P_AD8P_44 | Y12 | Bank 44 | I/O | User defined | |
| J3.106 | IO_L12N_AD8N_44 | FPGA.IO_L12N_AD8N_44 | AA12 | Bank 44 | I/O | User defined | |
| J3.108 | DGND | DGND | - | - | G | - | Digital ground |
| J3.110 | IO_L10P_AD10P_44 | FPGA.IO_L10P_AD10P_44 | Y14 | Bank 44 | I/O | User defined | |
| J3.112 | IO_L10N_AD10N_44 | FPGA.IO_L10N_AD10N_44 | Y13 | Bank 44 | I/O | User defined | |
| J3.114 | DGND | DGND | - | - | G | - | Digital ground |
| J3.116 | IO_L8P_HDGC_44 | FPGA.IO_L8P_HDGC_44 | AB15 | Bank 44 | I/O | User defined | |
| J3.118 | IO_L8N_HDGC_44 | FPGA.IO_L8N_HDGC_44 | AB14 | Bank 44 | I/O | User defined | |
| J3.120 | DGND | DGND | - | - | G | - | Digital ground |
| J3.122 | IO_L6P_HDGC_44 | FPGA.IO_L6P_HDGC_44 | AC14 | Bank 44 | I/O | User defined | |
| J3.124 | IO_L6N_HDGC_44 | FPGA.IO_L6N_HDGC_44 | AC13 | Bank 44 | I/O | User defined | |
| J3.126 | DGND | DGND | - | - | G | - | Digital ground |
| J3.128 | IO_L4P_AD12P_44 | FPGA.IO_L4P_AD12P_44 | AE13 | Bank 44 | I/O | User defined | |
| J3.130 | IO_L4N_AD12N_44 | FPGA.IO_L4N_AD12N_44 | AF13 | Bank 44 | I/O | User defined | |
| J3.132 | DGND | DGND | - | - | G | - | Digital ground |
| J3.134 | IO_L2P_AD14P_44 | FPGA.IO_L2P_AD14P_44 | AG14 | Bank 44 | I/O | User defined | |
| J3.136 | IO_L2N_AD14N_44 | FPGA.IO_L2N_AD14N_44 | AH14 | Bank 44 | I/O | User defined | |
| J3.138 | DGND | DGND | - | - | G | - | Digital ground |
| J3.140 | DGND | DGND | - | - | G | - | Digital ground |
