ONDA SOM/ONDA Hardware/Power and Reset/Reset scheme and control signals

History
Issue Date	Notes
2026/03/16	First documentation release
2026/03/26	Add clocks information

Reset scheme and control signals

The following picture shows the simplified block diagram of PSU, reset and control signals:

Signals description

The electrical and functional characteristics of reset and control signals are listed in the following table:

Signal	Type		Connector	Driven	Affect	Purpouse	Note
MRSTn	Open drain, User input	10kΩ pull-up on ONDA Refered to 3.3VIN rail	J2.116	Carrier	SOM PSU	ONDA performs COLD reset when MRSTn is asserted low.
CB_PGOOD	Open drain, User input	10kΩ pull-up on ONDA Refered to 3.3VIN rail	J2.110	Carrier	SOM PSU	ONDA initiates the power-up sequence when CB_PGOOD is released.
SOM_PGOOD	Open drain, User output	10kΩ pull-up on ONDA Refered to 3.3VIN rail	J2.108	SOM	Carrier PSU	ONDA indicates that the power sequence has been completed successfully. The carrier can now turn on the power supply voltages for the PL banks and its peripherals connected to the SOM.
PWR_ENABLE_xx	User monitor	Refered to 3.3VIN rail	J3.35, J3.70, J3.74, J3.78, J3.82, J3.86, J3.90	SOM PSU	-	Control signal that active the regulator on SOM.	See Pinout Table.
PWR_GOOD_xx	User monitor	Refered to 3.3VIN rail	J3.33, J3.72, J3.76, J3.80, J3.84, J3.88, J3.92	SOM PSU	-	Indicates that the regulator's output voltage has reached the rated value.	See Pinout Table.
PS_POR_B	Open drain, User output	4k7Ω pull-up on ONDA Refered to Bank503 rail (3.3V)	J2.114	SOM PSU	SoC & carrier	Zynq POR reset. This reset source does not cause a power cycle of SOM.
				WDT	SoC & carrier
PS_SRST_B	Open drain, User input	4k7Ω pull-up on ONDA Refered to Bank503 rail (3.3V)	J2.112	Carrier	SoC	Zynq external system reset. This reset source does not cause a power cycle of SOM.
SOM_PER_RSTn	Open drain, User output	10kΩ pull-up on ONDA Refered to 1.8V	J2.103	SOM	SOM memories & PHYs Carrier devices	ONDA resets their memories and PHYs when PS_POR_B or PS_SRST_B is asserted low.	Can be use as an input.

WDT

ONDA pairs the Zynq with a watchdog timer (WDT), Maxim MAX6373. The WDT output signal is connected to the PS_POR_B signal to trigger a warm reset if the timeout period is exceeded.

Whit a BOM variant, WDT can be trigger a cold reset by driving MRSTn signal: please contact sales dept. for more information.

For a detailed WDT description see the chapter Watchdog.

Clock scheme

ONDA is equipped with three independent active oscillators:

• processor (33.3 MHz)
• ethernet PHY (25 MHz)
• USB PHY (26 MHz)

Generally speaking, no clocks have to be provided by the carrier board.