ONDA SOM/ONDA Hardware/Peripherals/PS
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| 2026/03/25 | First documentation release | ||
Contents
Processing System[edit | edit source]
PS_MIO pins are multiplexed I/O that can be configured to support multiple I/O interfaces. These interfaces include QSPI, USB, Ethernet, SDIO, CAN, UART, SPI, and GPIO interfaces.
The MIO module, on ONDA SOM, are assigned as reported in the following table:
| MIO Pins | Bank | VCC | Function/Peripheral | Notes |
|---|---|---|---|---|
| [0:5] | B500 | 1V8 | QSPI0 | Internal connection to QSPI NOR flash |
| [7:12] | B500 | QSPI1 | Internal connection to QSPI NOR flash | |
| [13:22] | B500 | SD0 interface (eMMC) | Internal connection to eMMC | |
| [24:25] | B500 | UART1 | UART console | |
| [38:39] | B501 | 1V8
(or 3V3 with a BOM variant) |
I²C1 | Internal connection to RTC, EEPROM, Temperature Monitor |
| [40:41] | B501 | CAN1 | Internal connection to CAN PHY (optional bypass) | |
| [43:51] | B501 | SD1 (MMC) | External SD interface (boot) | |
| [52:63] | B502 | 1V8 | USB0 | Internal connection to USB PHY |
| [64:75] | B502 | Gigabit Ethernet 3 (GEM3) | Internal connection to ethernet PHY | |
| [76] | B502 | MDC (ethernet Management Data Clock input) | ||
| [77] | B502 | MDIO (ethernet Management Data Input/Output) | ||
| 23 | B500 | 1V8 | available on J1 | |
| [27:29], [31:37] | B501 | 1V8
(or 3V3 with a BOM variant) |
|
|
| 6 | B500 | 1V8 | unused MIO | Not connected |
| 26,30,42,44 | B501 | 1V8
(or 3V3 with a BOM variant) |
unused MIO | Not connected |
GT transceiver[edit | edit source]
These page reports the GT transceiver characteristics.
