ONDA SOM/ONDA Hardware/Peripherals/PS
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| History | |||
|---|---|---|---|
| Issue Date | Notes | ||
| First documentation release | |||
| 2026/06/10 | Update GT_transceiver and DDR information | ||
Contents
Processing System[edit | edit source]
PS_MIO pins are multiplexed I/O that can be configured to support multiple I/O interfaces. These interfaces include QSPI, USB, Ethernet, SDIO, CAN, UART, SPI, and GPIO interfaces.
The MIO module, on ONDA SOM, are assigned as reported in the following table:
| MIO Pins | Bank | VCC | Function/Peripheral | Notes |
|---|---|---|---|---|
| [0:5] | B500 | 1V8 | QSPI0 | Internal connection to QSPI NOR flash |
| [7:12] | QSPI1 | Internal connection to QSPI NOR flash | ||
| [13:22] | SD0 interface (eMMC) | Internal connection to eMMC | ||
| [24:25] | UART1 | UART console | ||
| [38:39] | B501 | 1V8
(or 3V3 with a BOM variant) |
I²C1 | Internal connection to RTC, EEPROM, Temperature Monitor |
| [40:41] | CAN1 | Internal connection to CAN PHY (optional bypass) | ||
| [43:51] | SD1 (MMC) | External SD interface (boot) | ||
| [52:63] | B502 | 1V8 | USB0 | Internal connection to USB PHY |
| [64:75] | Gigabit Ethernet 3 (GEM3) | Internal connection to ethernet PHY | ||
| [76] | MDC (ethernet Management Data Clock input) | Available on J1.89 | ||
| [77] | MDIO (ethernet Management Data Input/Output) | Available on J1.87 | ||
| 23 | B500 | 1V8 | unused MIO | Available on J1 |
| 6 | unrouted MIO | Not connected | ||
| [27:29], [31:37] | B501 | 1V8
(or 3V3 with a BOM variant) |
unused MIO | Available on J1 and J2 connectors (GPIOs)
Can be used as GPI/GPO for PMU |
| 26,30,42,44 | unrouted MIO | Not connected |
GT transceiver[edit | edit source]
The following table reports the GT transceiver characteristics:
| FPGA Bank | Type | Differentials Pairs | Clock pairs | |||
|---|---|---|---|---|---|---|
| XCZU4 /
XCZU5 |
XCZU3T | XCZU2 | XCZU1 | |||
| Bank 505 | GTR | 4 | 4 | 4 | 4 | 1 |
- GTR = PS-GTR receivers and transmitters supports up to 6.0Gb/s data rates (supports SGMII tri-speed Ethernet, PCI Express® Gen2, Serial-ATA (SATA), USB3.0, and DisplayPort™)
DDR[edit | edit source]
The B504 bank is interfaced with DDR4 memories configured at 64-bit with 8-bit ECC.
For implementation details, see UG1085-TRM ch.17.3.4 "Error Correcting Code".
