ONDA SOM/ONDA Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence

History
Issue Date	Notes
2026/03/24	First documentation release
2026/05/14	Add input power info

Power Supply Unit (PSU) and recommended power-up sequence

Implementing a correct power-up sequence for Zynq Ultrascale+ processors is not a trivial task because several power rails are involved.

ONDA SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU circuitry:

The PSU:

• consists of several regulators for each SOC power rail
• generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals
• synchronizes the powering up of the carrier board to prevent back power
• continuously checks the correct voltages of the various power rails

The picture also shows the control signals involved: for a detailed description see the chapter Reset scheme and control signals.

Input power

ONDA SoM has two input power rails, which the carrier board must supply. When these rails are stable, the carrier board raises CB_PGOOD signal to indicate to the SoM that it can start its power-up sequence.

For simplicity or backward compatibility with BORA or BORAX products, both rails can be supplied with the same 3.3V source.

Main power

Through 15 pins on J2 connector.

This rail provides the power required by the SoC.

Its voltage can be 3.3V or 5V, the latter chosen to reduce the input current.

Auxiliary power

Through 3 pins on J2 connector.

This rail powers the SoM's auxiliary circuits such as the PSU supervisor, power sequencer, reset circuit and WDT.

This rail is fixed at 3.3V, in order to harmonize the PSU control circuitry on the carrier board.

Power-up sequence

The recommended power-up sequence is:

1. Carrier board generate main and auxiliary SOM power supply rails (VIN and 3.3VIN)
2. Carrier board circuitry raises CB_PGOOD signal when VIN and 3.3VIN rails are stable (see note)
3. ONDA's PSU enables and sequences DC/DC regulators to turn on the rails
4. ONDA raises SOM_PGOOD signal; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa)
5. Finally, ONDA release PS_POR_B signal (see Reset scheme and control signals)

Please note that FPGA Bank 43, 43, 65 and 66 of the PL must be powered by carrier board, even if they are not used to implement any function. Three dedicated power rails are available for this purpose (VDDIO_BANK43-34, VDDIO_BANK65 and VDDIO_BANK66), offering the system designer the freedom to select the I/O voltage of these three banks. The power rails of these banks are enabled by the SOM_PGOOD signal and are connected to the I/O power supply rail provided by the carrier board.

N.B.: Regarding power off, it is recommended that I/O supply is turned off before core supply.

Cold reset

To force a cold reset, which shuts down all regulators on the SOM and restarts the power-up sequence, force the MRSTn signal to low for a few hundred of milliseconds.

Note on CB_PGOOD

The step 2 of power sequence is not mandatory and CB_PGOOD can be left floating.

CB_PGOOD is provided to prevent, if necessary, ONDA's PSU to turn on during ramp or glitch of VIN and 3.3VIN rails.

This signal is referenced to 3.3VIN auxiliary input PS; when the signal rises, the SoM power-up sequence begins.

Note on SOM_PGOOD

SOM_PGOOD signal (active-high) indicates that SoM's I/O is powered: use this signal to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa).

This signal is referenced to 3.3VIN auxiliary input PS.

SOM_PGOOD signal rises about 2 ms after the last SoC rail is activated. Then, after about 4 ms, the PS_POR_B signal is release.

The carrier must turn on its rails related to the SoC's PS-PL signals before the PS_POR_B signal is released. If this time interval is not sufficient, force low the PS_POR_B on the carrier board its power-up sequence is completed.

Note on embedding power sequence circuitry

The sequential switching on of the different voltage regulators is controlled and monitored, for each rail, by a pair of signals called 'Power enable' and 'Power good': these pairs of signals can be monitored at connector J3.