ONDA Plus SOM/ONDA Plus Hardware/pdf

General Information

BORA Block Diagram

ONDA Plus Block diagram

BORA TOP View

ONDA Plus TOP View

BORA BOTTOM View

ONDA Plus BOTTOM View

Processor and memory subsystem

The heart of ONDA Plus module is composed by the following components:

• Xilinx Zynq Ultrascale+ XCZU6EG / XCZU9EG or XCZU15EG SoC
• Power supply unit
• DDR memory banks
• NOR and eMMC flash storage
• 3x 240 pin connectors with interfaces signals

This chapter shortly describes the main ONDA Plus components.

Processor Info

Table: XCZUxxEG models comparison

Processor	XCZUxxEG
# Cores	4x Arm® Cortex®-A53 2x Arm® Cortex®-MRF
Clocks	Cortex®-A53 up to 1.5 GHz Cortex®-MRF up to 600 MHz
L2 Cache	1 MB
OchChip RAM	256 KB
DDR4	64 bit @ 2400 MHz
GPU	ARM Mali-400 up to 667 MHz OpenGL ES 1.1 and Open VG 1.1
Ethernet	1 Gbit/s MAC (with 3 additional RGMII)
PCIe	x1, x2 and x4 Gen2 (2.1 base specification)
USB	USB 2.0
Serial Interfaces	UART, CAN, I2C, SPI

PL info

The Zynq™Ultrascale+ MPSoCs have software, hardware, interconnect, power, security, and I/O programmability. The range of devices in the Zynq UltraScale+ MPSoC family allows designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools.

The Zynq UltraScale+ MPSoCs are able to serve a wide range of applications including:

• Automotive: Driver assistance, driver information, and infotainment
• Wireless Communications: Support for multiple spectral bands and smart antennas
• Wired Communications: Multiple wired communications standards and context-aware network services
• Data Centers: Software Defined Networks (SDN), data pre-processing, and analytics
• Smarter Vision: Evolving video-processing algorithms, object detection, and analytics
• Connected Control/M2M: Flexible/adaptable manufacturing, factory throughput, quality, and safet

ONDA Plus can mount three versions of the Zynq US+ processor. The following table shows the main PL features:

Table: XCZUxxEG features

Processor	Programmable logic cells	LUTs	Flip flops	Distributed RAM	Total Block RAM	DSP slices	Serial Tranceivers	Peak Serial Transceiver performance
XCZU6EG	469K Logic Cells	214604	429208	6.9 Mb	25.1 Mb	1973	4	10 Gb/s (*)
XCZU9EG	600K Logic Cells	274080	548160	8.8 Mb	32.1 Mb	2520	4	10 Gb/s (*)
XCZU15EG	746K Logic Cells	341280	682560	11.3 Mb	26.2 Mb	3528	4	10 Gb/s (*)

(*) tested connectors bandwidth

RAM memory bank

DDR4 RAM memory bank is composed by 64-bit width chips. The following table reports the RAM specifications:

CPU connection	Dynamic Memory Controller (DDRC)
Size max	16 GB
Width	64 bit with hardware ECC
Speed	3200 MHz

NOR flash bank

NOR flash is a Serial Peripheral Interface (SPI) device. By default two devices are connected to both QSPI channel 0 and channel 1 for a dual parallel interface. They acts as boot memory. The following table reports the NOR flash specifications:

CPU connection	PS MIO QSPI Channel 0 / 1
Size min	16 MB
Size max	32 MB
Chip select	SS5 and SS7
Bootable	Yes

eMMC flash bank

On board main storage memory eMMC is connected to the PS MIO interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:

CPU connection	PS MIO SDIO0
Size min	8 GB
Size max	128 GB
Bootable	Yes

Power supply unit

ONDA Plus embeds all the elements required for powering the unit, so the power sequencing is self-contained and simplified. Nevertheless, power must be provided from the carrier board, and therefore users should be aware of the power supply ranges that can be assumed as well as all other parameters.

Hardware versioning and tracking

ONDA Plus SOM implements well established versioning and tracking mechanisms:

• PCB version is copper printed on PCB itself, as shown in Fig. 1
• serial number: it is printed on a white label, as shown in Fig. 2: see also Product serial number page for more details
• ConfigID: it is used by software running on the board for the identification of the product model/hardware configuration. For more details, please refer to this link
  • on ONDA Plus SOM ConfigID is stored in an internal I2C EEPROM

Fig.1 PCB version

Fig.2 Serial number

Part number composition

ONDA Plus SOM module part number is identified by the following digit-code table:

Part number structure	Options	Description
Family	NDP	Family prefix code
SOC	0: XCZU6EG Quad-core Cortex-A53 @1.5 GHz, Dual-core Cortex-R5F @600 MHz 1: XCZU9EG Quad-core Cortex-A53 @1.5 GHz, Dual-core Cortex-R5F @600 MHz 2: XCZU15EG Quad-core Cortex-A53 @1.5 GHz, Dual-core Cortex-R5F @600 MHz 3: XQZU9EG Quad-core Cortex-A53 @1.5 GHz, Dual-core Cortex-R5F @600 MHz 4: XQZU15EG Quad-core Cortex-A53 @1.5 GHz, Dual-core Cortex-R5F @600 MHz	Other versions can be available, please contact technical support
RAM	4: 4GB DDR4 with ECC
Storage	0: 128GB eMMC pSLC and 32MB NOR
RFU	0: Default
Mounting options	0: PL banks 47, 48, 64, 65, 66 1V8 fixed 1: PL banks 47, 48 @1V8, 64, 65, 66 1V8 external power supply
Temperature range	C - Commercial grade: suitable for 0-70°C environment I - Industrial grade: suitable for 40 - 85°C environment
PCB revision	0: first version 1: PCB rev. A	PCB release may change for manufacturing purposes (i.e. text fixture adaptation)
Manufacturing option	N: No-RoHS R: RoHS compliant S: Leaded (SnPb) No-RoHS	typically connected to production process and quality
Software Configuration	-00: standard factory u-boot pre-programmed	If customers require custom SW deployed this section should be defined and agreed. Please contact technical support

Example

ONDA PLUS SOM code NDP44001I1R-00

• 4: XQZU15EG Quad core A53 1.5GHz / Dual core R5F
• 4: 4GB DDR4
• 0: 128GB eMMC and 32MB NOR
• 0: -
• 1: PL banks 47, 48 @1V8, 64, 65, 66 1V8 external power supply
• I: Industrial grade: -40 to +85°C
• 1: PCB version rev. A
• R: RoHS compliant
• -00: standard factory u-boot pre-programmed

Pinout Table

Connectors and Pinout Table

This chapter contains the pinout description of the ONDA Plus module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 240-pin ONDA Plus connectors.

Connectors description

In the following table are described the interface connectors on ONDA Plus SOM:

Connector name	Connector Type	Notes	Carrier board counterpart
J1, J2, J3	Samtec ADM6-60-01.5-L-4-2-A-TR 3x240 pins 0.65 mm pitch connectors		Samtec ADF6-60-03.5-L-4-2-A-TR

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to ONDA Plus pinout specifications. See the images below for reference:

ONDA Plus BOTTOM view - J1,J2,J3 connectors' rows indications (pins A1-B1-C1-D1)

Pinout table naming conventions

Each row in the pinout tables contains the following information:

• CPU.<x> : pin connected to CPU (processing system) pad named <x>
• FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
• CAN.<x> : pin connected to the CAN transceiver TCAN3413DR
• LAN.<x> : pin connected to the LAN PHY LAN8830
• USB.<x> : pin connected to the USB transceiver USB3317C
• EEPROM.<x>: pin connected to the EEPROM 24LC32AT
• RTC.<x>: pin connected to the Real Time Clock DS3232MZ+
• WD.<x>: pin connected to the Watchdog MAX6373KA+
• PSUM.<x>: pin connected to the main Step Down power module LTM4638EY
• PSU.<x>: pin connected to the Step Down power module TPSM828303
• PSUS.<x>: pin connected to the power switch TPS22965DSGR
• PSUL.<x>: pin connected to the LDO TPS74801DRCR
• PSUD.<x>: pin connected to the DDR regulator TPS51206DSQR

Pin	reference to the connector pin
Pin Name	Pin (signal) name on the ONDA Plus connectors
Internal connections	Connections to the ONDA Plus components
Ball/pin #	Component ball/pin number connected to signal
Voltage (see here)	I/O voltage levels 1.8V 3.3V U.D. = User Defined
Type	Pin type I = Input O = Output D = Differential Z = High impedance S = Power supply voltage G = Ground A = Analog signal A/G = Analog Ground

SOM J1A pins (A1 to A60 - B1 to B60) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J1.A1	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.A2	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.A3	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.A4	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.A5	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.A6	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.A7	DGND	DGND	-	-	G	-	Digital ground
J1.A8	DGND	DGND	-	-	G	-	Digital ground
J1.A9	DGND	DGND	-	-	G	-	Digital ground
J1.A10	DGND	DGND	-	-	G	-	Digital ground
J1.A11	1.8V_IO	1.8V_IO	-	1.8V	S		1.8V internal PSU stage
J1.A12	TSNSA_P	PSUM.TSNSA_P	A6	3.3V_IN	S
J1.A13	TSNSA_N	PSUM.TSNSA_N	A7	3.3V_IN	S
J1.A14	DGND	DGND	-	-	G	-	Digital ground
J1.A15	TSNSB_P	PSUM.TSNSB_P	A6	3.3V_IN	S
J1.A16	TSNSB_N	PSUM.TSNSB_N	A7	3.3V_IN	S
J1.A17	AGND	AGND	-	-	G	-	Analog ground
J1.A18	ADC_P	FPGA.VP	U16	Bank 503	A		Optionally available as a mount option
J1.A19	ADC_N	FPGA.VN	V15	Bank 503	A		Optionally available as a mount option
J1.A20	DGND	DGND	-	-	G	-	Digital ground
J1.A21	PS_MODE0	CPU.PS_MODE0	CPU.U18	Bank 503	I/O	1.8V	This signal is pulled up or down with 1kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[0]=0)
J1.A22	PS_MODE1	CPU.PS_MODE1	CPU.U19	Bank 503	I/O	1.8V	This signal is pulled up or down with 1kOhm resistor to select proper bootstrap configuration. Default configuration: pull-up (BOOT_MODE[1]=1)
J1.A23	PS_MODE2	CPU.PS_MODE2	CPU.U20	Bank 503	I/O	1.8V	This signal is pulled up or down with 1kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[2]=0)
J1.A24	PS_MODE3	CPU.PS_MODE3	CPU.U21	Bank 503	I/O	1.8V	This signal is pulled up or down with 1kOhm resistor to select proper bootstrap configuration. Default configuration: pull-down (BOOT_MODE[3]=0)
J1.A25	DGND	DGND	-	-	G	-	Digital ground
J1.A26	PS_SRST_B	CPU.PS_SRST_B	P19	Bank 503	I	1.8V	Internally connected to Bank 503 power supply via 10K resistor For further details, please refer to Reset scheme
J1.A27	PS_POR_B	CPU.PS_POR_B WD.WDOn	U23 7	Bank 503	I/O	1.8V	Internally connected to Bank 503 power supply via 10K resistor For further details, please refer to Reset scheme
J1.A28	WD_RST	WDT.RST	7	3.3V	I	3.3V	For further details, please refer to Reset scheme
J1.A29	PS_POR_OVERRIDE	CPU.PS_POR_OVERRIDE	AB14	Bank 503	I/O	1.8V	Internally connected to Bank 503 power supply via 10K resistor For further details, please refer to Reset scheme
J1.A30	PUDC_B	CPU.PUDC_B	AB15	Bank 503	I/O	1.8V	Internally connected to Bank 503 power supply via 10K resistor For further details, please refer to Reset scheme
J1.A31	DGND	DGND	-	-	G	-	Digital ground
J1.A32	PS_DONE	FPGA.PS_DONE	T18	Bank 503	I/O	1.8V	For further details, please refer to PL initialization signals (10 kohm pull-up resistor is already mounted on ONDA Plus SOM)
J1.A33	PS_PROG_B	FPGA.PS_PROG_B	T22	Bank 503	I	1.8V	For further details, please refer to PL initialization signals (10 kohm pull-up resistor is already mounted on ONDA Plus SOM)
J1.A34	PS_INIT_B	FPGA.PS_INIT_B	T23	Bank 503	I/O	1.8V	For further details, please refer to PL initialization signals
J1.A35	PS_ERROR_OUT	CPU.PS_ERROR_OUT	CPU.P21	Bank 503	I/O	1.8V	This signal has an optional internal pull-up (10k)
J1.A36	PS_ERROR_STATUS	CPU.PS_ERROR_STATUS	CPU.P22	Bank 503	I/O	1.8V	This signal has an internal pull-up (10k)
J1.A37	DGND	DGND	-	-	G	-	Digital ground
J1.A38	JTAG_TMS	CPU.PS_JTAG_TMS	R19	Bank 503	I	1.8V
J1.A39	JTAG_TDO	CPU.PS_JTAG_TDO	T20	Bank 503	O	1.8V
J1.A40	JTAG_TDI	CPU.PS_JTAG_TDI	T21	Bank 503	I	1.8V
J1.A41	JTAG_TCK	CPU.PS_JTAG_TCK	R20	Bank 503	I	1.8V
J1.A42	DGND	DGND	-	-	G	-	Digital ground
J1.A43	WD_SET0	WDT.SET0	4	3.3V	I	3.3V
J1.A44	WD_SET1	WDT.SET1	5	3.3V	I	3.3V
J1.A45	WD_SET2	WDT.SET2	6	3.3V	I	3.3V
J1.A46	WDT_REARM	WD.WDI	1	3.3V_IN	I	-	Watchdog rearm pin
J1.A47	DGND	DGND	-	-	G	-	Digital ground
J1.A48	RTC_VBAT	RTC.VBAT	6	-	S	-
J1.A49	RTC_32KHZ	RTC.32KHZ	1	3.3V	O	3.3V
J1.A50	RTC_INTn/SQW	RTC.INT/SQW	3	3.3V	I/O	3.3V	It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.
J1.A51	RTC_RSTn	RTC.RSTn	4	3.3V	I/O	3.3V
J1.A52	DGND	DGND	-	-	G	-	Digital ground
J1.A53	I2C0_SCL	-	-	3.3V	I/O	3.3V
J1.A54	I2C0_SDA	-	-	3.3V	I/O	3.3V
J1.A55	PS_MIO38_501	CPU.PS_MIO38_501	F20	Bank 501	I/O	3.3V / User defined
J1.A56	PS_MIO39_501	CPU.PS_MIO39_501	H19	Bank 501	I/O	3.3V / User defined
J1.A57	DGND	DGND	-	-	G	-	Digital ground
J1.A58	PS_MIO24_500	CPU.PS_MIO24_500	J16	Bank 500	I/O	1.8V
J1.A59	PS_MIO25_500	CPU.PS_MIO25_500	G16	Bank 500	I/O	1.8V
J1.A60	DGND	DGND	-	-	G	-	Digital ground

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J1.B1	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.B2	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.B3	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.B4	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.B5	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.B6	3.3V_IN	3.3V_IN	-	3.3V_IN	S		3.3V Power Supply
J1.B7	DGND	DGND	-	-	G	-	Digital ground
J1.B8	DGND	DGND	-	-	G	-	Digital ground
J1.B9	DGND	DGND	-	-	G	-	Digital ground
J1.B10	DGND	DGND	-	-	G	-	Digital ground
J1.B11	VBAT	CPU.VCC_PSBATT	AA23	-	S	-	Internally connected to 1.8V_IO
J1.B12	SOM_PGOOD		n.a.	3.3V	O	3.3V	Internally connected to 3.3V_IN via 10K resistor For further details, please refer to Power_Supply_Unit
J1.B13	EEPROM_WP	EEPROM.WP	7			3.3V
J1.B14	DGND	DGND	-	-	G	-	Digital ground
J1.B15	EN_0V85_INT	PSUM.B4	-	3.3V_IN	I	-	Power Enable for 0V85 INT power supply LDO regulator
J1.B16	PG_0V85_INT	PSUM.B5	-	3.3V_IN	O	-	Power Good for 0V85 INT power supply LDO regulator
J1.B17	EN_1V8_AUX	PSU.9	-	3.3V_IN	I	-	Power Enable for 1V8 AUX power supply regulator
J1.B18	PG_1V8_AUX	PSU.7	-	3.3V_IN	O	-	Power Good for 1V8 AUX power supply regulator
J1.B19	EN_1V2_GTH	PSU.9	-	VIN	I	-	Power Enable for 1V2 GTH power supply regulator
J1.B20	PG_1V2_GTH	PSU.7	-	3.3V_IN	O	-	Power Good for 1V2 GTH power supply regulator
J1.B21	EN_2V5_PP	PSU.9	-	3.3V_IN	I	-	Power Enable for 2V5 power supply regulator
J1.B22	PG_2V5_PP	PSU.7	-	3.3V_IN	O	-	Power Good for 2V5 power supply regulator
J1.B23	EN_1V2_DDR	PSU.9	-	3.3V_IN	I	-	Power Enable for 1V2 DDR power supply regulator
J1.B24	PG_1V2_DDR	PSU.7	-	3.3V_IN	O	-	Power Good for 1V2 DDR power supply regulator
J1.B25	EN_0V85_MGT	PSUL.5	-	1.2V	I	-	Power Enable for 0V85 GTR power supply LDO regulator
J1.B26	PG_0V85_MGT	PSUL.3	-	1.2V	O	-	Power Good for 0V85 GTR power supply LDO regulator
J1.B27	EN_1V8_IO	PSU.9	-	3.3V_IN	I	-	Power Enable for 1V8 I/O power supply regulator
J1.B28	PG_1V8_IO	PSU.7	-	3.3V_IN	I	-	Power Godd for 1V8 I/O power supply regulator
J1.B29	EN_0V9_GTH	PSU.9	-	3.3V_IN	I	-	Power Enable for 0V9 GTH power supply LDO regulator
J1.B30	PG_0V9_GTH	PSU.7	-	3.3V_IN	O	-	Power Good for 0V9 GTH power supply LDO regulator
J1.B31	EN_0V6_VTT	PSUD.7	-	1.2V	I	-	Power Enable for 0V6 VTT power supply LDO regulator
J1.B32	DGND	DGND	-	-	G	-	Digital ground
J1.B33	USB_RSTn	USB.RESETB	22		I	1.8V	Internally connected to USB_VDDIO via 10K resistor
J1.B34	USB_VBUS	USB.VBUS	2
J1.B35	USB_CPEN	USB.CPEN	7			3.3V
J1.B36	USB_ID	USB.ID	1
J1.B37	DGND	DGND	-	-	G	-	Digital ground
J1.B38	USB_D_P	USB.DP	6		D
J1.B39	USB_D_N	USB.DM	5		D
J1.B40	DGND	DGND	-	-	G	-	Digital ground
J1.B41	ETH_INTn	LAN.ETH_INTn	9		D
J1.B42	ETH_RSTn	LAN.RESET_N	43		I	1.8V	Internally connected to ETH_VDDIO via 10K resistor and to SOM_PER_RSTn
J1.B43	ETH_LED5	LAN.LED5	13	-		1.8V
J1.B44	ETH_LED4	LAN.LED4	14	-		1.8V
J1.B45	ETH_LED3	LAN.LED3	15	-		1.8V
J1.B46	ETH_LED2	LAN.LED2	16	-		1.8V
J1.B47	ETH_LED1	LAN.LED1	18	-		1.8V
J1.B48	DGND	DGND	-	-	G	-	Digital ground
J1.B49	ETH_TXRX0_N	LAN.ETH_TXRX0M_A	3		D
J1.B50	ETH_TXRX0_P	LAN.ETH_TXRX0P_A	2		D
J1.B51	DGND	DGND	-	-	G	-	Digital ground
J1.B52	ETH_TXRX1_N	LAN.TXRXM_B	6		D
J1.B53	ETH_TXRX1_P	LAN.TXRXP_B	5		D
J1.B54	DGND	DGND	-	-	G	-	Digital ground
J1.B55	ETH_TXRX2_N	LAN.TXRXM_C	8		D
J1.B56	ETH_TXRX2_P	LAN.TXRXP_C	7		D
J1.B57	DGND	DGND	-	-	G	-	Digital ground
J1.B58	ETH_TXRX3_N	LAN.TXRXM_D	11		D
J1.B59	ETH_TXRX3_P	LAN.TXRXP_D	10		D
J1.B60	DGND	DGND	-	-	G	-	Digital ground

SOM J1B pins (C1 to C60 - D1 to D60) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J1.C1	PS_MGTREFCLK0P_505	CPU.PS_MGTREFCLK0P_505	P25	0V85	D
J1.C2	PS_MGTREFCLK0N_505	CPU.PS_MGTREFCLK0P_505	P26	0V85	D
J1.C3	DGND	DGND	-	-	G	-	Digital ground
J1.C4	PS_MGTREFCLK2P_505	CPU.PS_MGTREFCLK2P_505	K25	0V85	D
J1.C5	PS_MGTREFCLK2N_505	CPU.PS_MGTREFCLK2P_505	K26	0V85	D
J1.C6	DGND	DGND	-	-	G	-	Digital ground
J1.C7	PS_MGTRTXP0_505	CPU.PS_MGTRTXP0_505	R27	0V85	I/O
J1.C8	PS_MGTRTXN0_505	CPU.PS_MGTRTXN0_505	R28	0V85	I/O
J1.C9	DGND	DGND	-	-	G	-	Digital ground
J1.C10	PS_MGTRTXP2_505	CPU.PS_MGTRTXP2_505	L27	0V85	I/O
J1.C11	PS_MGTRTXN2_505	CPU.PS_MGTRTXN2_505	L28	0V85	I/O
J1.C12	DGND	DGND	-	-	G	-	Digital ground
J1.C13	PS_MGTRRXP0_505	CPU.PS_MGTRRXP0_505	T29	0V85	I/O
J1.C14	PS_MGTRRXN0_505	CPU.PS_MGTRRXN0_505	T30	0V85	I/O
J1.C15	DGND	DGND	-	-	G	-	Digital ground
J1.C16	PS_MGTRRXP2_505	CPU.PS_MGTRRXP2_505	M29	0V85	I/O
J1.C17	PS_MGTRRXN2_505	CPU.PS_MGTRRXN2_505	M30	0V85	I/O
J1.C18	DGND	DGND	-	-	G	-	Digital ground
J1.C19	DGND	DGND	-	-	G	-	Digital ground
J1.C20	DGND	DGND	-	-	G	-	Digital ground
J1.C21	PS_MIO23	CPU.PS_MIO23_500	F16	Bank 500	I/O	1.8V	MIO23 pin
J1.C22	DGND	DGND	-	-	G	-	Digital ground
J1.C23	PS_MIO26	CPU.PS_MIO26_501	A19	Bank 501	I/O	3.3V / User defined	MIO26 pin
J1.C24	PS_MIO27	CPU.PS_MIO27_501	C19	Bank 501	I/O	3.3V / User defined	MIO27 pin
J1.C25	PS_MIO28	CPU.PS_MIO28_501	B19	Bank 501	I/O	3.3V / User defined	MIO28 pin
J1.C26	PS_MIO29	CPU.PS_MIO29_501	E19	Bank 501	I/O	3.3V / User defined	MIO29 pin
J1.C27	DGND	DGND	-	-	G	-	Digital ground
J1.C28	PS_MIO30	CPU.PS_MIO30_501	D19	Bank 501	I/O	3.3V / User defined	MIO30 pin
J1.C29	PS_MIO31	CPU.PS_MIO31_501	J19	Bank 501	I/O	3.3V / User defined	MIO31 pin
J1.C30	PS_MIO32	CPU.PS_MIO32_501	K19	Bank 501	I/O	3.3V / User defined	MIO32 pin
J1.C31	PS_MIO33	CPU.PS_MIO33_501	M19	Bank 501	I/O	3.3V / User defined	MIO33 pin
J1.C32	DGND	DGND	-	-	G	-	Digital ground
J1.C33	PS_MIO34	CPU.PS_MIO34_501	D20	Bank 501	I/O	3.3V / User defined	MIO34 pin
J1.C34	PS_MIO35	CPU.PS_MIO35_501	N19	Bank 501	I/O	3.3V / User defined	MIO35 pin
J1.C35	PS_MIO36	CPU.PS_MIO36_501	E20	Bank 501	I/O	3.3V / User defined	MIO36 pin
J1.C36	PS_MIO37	CPU.PS_MIO37_501	B20	Bank 501	I/O	3.3V / User defined	MIO37 pin
J1.C37	DGND	DGND	-	-	G	-	Digital ground
J1.C38	PS_MIO40	CPU.PS_MIO38_501	G20	Bank 501	I/O	3.3V / User defined	MIO40 pin
J1.C39	PS_MIO41	CPU.PS_MIO39_501	K20	Bank 501	I/O	3.3V / User defined	MIO41 pin
J1.C40	DGND	DGND	-	-	G	-	Digital ground
J1.C41	PS_MIO42	CPU.PS_MIO42_501	M20	Bank 501	I/O	3.3V / User defined	MIO42 pin
J1.C42	PS_MIO43	CPU.PS_MIO43_501	L20	Bank 501	I/O	3.3V / User defined	MIO43 pin
J1.C43	PS_MIO44	CPU.PS_MIO44_501	A20	Bank 501	I/O	3.3V / User defined	MIO44 pin
J1.C44	PS_MIO45	CPU.PS_MIO45_501	A21	Bank 501	I/O	3.3V / User defined	MIO45 pin
J1.C45	DGND	DGND	-	-	G	-	Digital ground
J1.C46	PS_MIO46	CPU.PS_MIO46_501	B21	Bank 501	I/O	3.3V / User defined	MIO46 pin
J1.C47	PS_MIO47	CPU.PS_MIO47_501	D21	Bank 501	I/O	3.3V / User defined	MIO47 pin
J1.C48	PS_MIO48	CPU.PS_MIO48_501	F21	Bank 501	I/O	3.3V / User defined	MIO48 pin
J1.C49	PS_MIO49	CPU.PS_MIO49_501	C21	Bank 501	I/O	3.3V / User defined	MIO49 pin
J1.C50	DGND	DGND	-	-	G	-	Digital ground
J1.C51	PS_MIO50	CPU.PS_MIO50_501	G21	Bank 501	I/O	3.3V / User defined	MIO50 pin
J1.C52	PS_MIO51	CPU.PS_MIO51_501	J20	Bank 501	I/O	3.3V / User defined	MIO51 pin
J1.C53	DGND	DGND	-	-	G	-	Digital ground
J1.C54	DGND	DGND	-	-	G	-	Digital ground
J1.C55	DGND	DGND	-	-	G	-	Digital ground
J1.C56	DGND	DGND	-	-	G	-	Digital ground
J1.C57	VDDIO_BANK501	FPGA.VCCO_501	L19 H20 E21	Bank 501	S	3.3V / User defined	Bank501 I/O Power Supply
J1.C58	VDDIO_BANK501	FPGA.VCCO_501	L19 H20 E21	Bank 501	S	3.3V / User defined	Bank501 I/O Power Supply
J1.C59	VDDIO_BANK501	FPGA.VCCO_501	L19 H20 E21	Bank 501	S	3.3V / User defined	Bank501 I/O Power Supply
J1.C60	VDDIO_BANK501	FPGA.VCCO_501	L19 H20 E21	Bank 501	S	3.3V / User defined	Bank501 I/O Power Supply

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J1.D1	DGND	DGND	-	-	G	-	Digital ground
J1.D2	PS_MGTREFCLK1P_505	CPU.PS_MGTREFCLK1P_505	M25	0V85	D
J1.D3	PS_MGTREFCLK1N_505	CPU.PS_MGTREFCLK1P_505	M26	0V85	D
J1.D4	DGND	DGND	-	-	G	-	Digital ground
J1.D5	PS_MGTREFCLK3P_505	CPU.PS_MGTREFCLK3P_505	H25	0V85	D
J1.D6	PS_MGTREFCLK3N_505	CPU.PS_MGTREFCLK3P_505	H26	0V85	D
J1.D7	DGND	DGND	-	-	G	-	Digital ground
J1.D8	PS_MGTRTXP1_505	CPU.PS_MGTRTXP1_505	N27	0V85	I/O
J1.D9	PS_MGTRTXN1_505	CPU.PS_MGTRTXN1_505	N28	0V85	I/O
J1.D10	DGND	DGND	-	-	G	-	Digital ground
J1.D11	PS_MGTRTXP3_505	CPU.PS_MGTRTXP3_505	J27	0V85	I/O
J1.D12	PS_MGTRTXN3_505	CPU.PS_MGTRTXN3_505	J28	0V85	I/O
J1.D13	DGND	DGND	-	-	G	-	Digital ground
J1.D14	PS_MGTRRXP1_505	CPU.PS_MGTRRXP1_505	D27	Bank 505	I/O
J1.D15	PS_MGTRRXN1_505	CPU.PS_MGTRRXN1_505	D28	Bank 505	I/O
J1.D16	DGND	DGND	-	-	G	-	Digital ground
J1.D17	PS_MGTRRXP3_505	CPU.PS_MGTRRXP3_505	J27	Bank 505	I/O
J1.D18	PS_MGTRRXN3_505	CPU.PS_MGTRRXN3_505	J28	Bank 505	I/O
J1.D19	DGND	DGND	-	-	G	-	Digital ground
J1.D20	DGND	DGND	-	-	G	-	Digital ground
J1.D21	PS_MIO00	CPU.PS_MIO00_500	C18	Bank 500	I/O	1.8V	MIO00 pin
J1.D22	PS_MIO01	CPU.PS_MIO01_500	H17	Bank 500	I/O	1.8V	MIO01 pin
J1.D23	PS_MIO02	CPU.PS_MIO02_500	E18	Bank 500	I/O	1.8V	MIO02 pin
J1.D24	PS_MIO03	CPU.PS_MIO03_500	F18	Bank 500	I/O	1.8V	MIO03 pin
J1.D25	PS_MIO04	CPU.PS_MIO04_500	G18	Bank 500	I/O	1.8V	MIO04 pin
J1.D26	PS_MIO05	CPU.PS_MIO05_500	J17	Bank 500	I/O	1.8V	MIO05 pin
J1.D27	PS_MIO06	CPU.PS_MIO06_500	H18	Bank 500	I/O	1.8V	MIO06 pin
J1.D28	DGND	DGND	-	-	G	-	Digital ground
J1.D29	DGND	DGND	-	-	G	-	Digital ground
J1.D30	DGND	DGND	-	-	G	-	Digital ground
J1.D31	DGND	DGND	-	-	G	-	Digital ground
J1.D32	DGND	DGND	-	-	G	-	Digital ground
J1.D33	DGND	DGND	-	-	G	-	Digital ground
J1.D34	DGND	DGND	-	-	G	-	Digital ground
J1.D35	DGND	DGND	-	-	G	-	Digital ground
J1.D36	DGND	DGND	-	-	G	-	Digital ground
J1.D37	DGND	DGND	-	-	G	-	Digital ground
J1.D38	DGND	DGND	-	-	G	-	Digital ground
J1.D39	DGND	DGND	-	-	G	-	Digital ground
J1.D40	DGND	DGND	-	-	G	-	Digital ground
J1.D41	DGND	DGND	-	-	G	-	Digital ground
J1.D42	DGND	DGND	-	-	G	-	Digital ground
J1.D43	DGND	DGND	-	-	G	-	Digital ground
J1.D44	DGND	DGND	-	-	G	-	Digital ground
J1.D45	DGND	DGND	-	-	G	-	Digital ground
J1.D46	DGND	DGND	-	-	G	-	Digital ground
J1.D47	DGND	DGND	-	-	G	-	Digital ground
J1.D48	DGND	DGND	-	-	G	-	Digital ground
J1.D49	DGND	DGND	-	-	G	-	Digital ground
J1.D50	DGND	DGND	-	-	G	-	Digital ground
J1.D51	DGND	DGND	-	-	G	-	Digital ground
J1.D52	DGND	DGND	-	-	G	-	Digital ground
J1.D53	DGND	DGND	-	-	G	-	Digital ground
J1.D54	DGND	DGND	-	-	G	-	Digital ground
J1.D55	DGND	DGND	-	-	G	-	Digital ground
J1.D56	DGND	DGND	-	-	G	-	Digital ground
J1.D57	DGND	DGND	-	-	G	-	Digital ground
J1.D58	DGND	DGND	-	-	G	-	Digital ground
J1.D59	DGND	DGND	-	-	G	-	Digital ground
J1.D60	DGND	DGND	-	-	G	-	Digital ground

SOM J2A pins (A1 to A60 - B1 to B60) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J2.A1	VDDIO_BANK47	FPGA.VCCO_47	J13 H15	Bank 47	S	1.8V / User defined	Bank47 I/O Power Supply
J2.A2	VDDIO_BANK47	FPGA.VCCO_47	J13 H15	Bank 47	S	1.8V / User defined	Bank47 I/O Power Supply
J2.A3	VDDIO_BANK47	FPGA.VCCO_47	J13 H15	Bank 47	S	1.8V / User defined	Bank47 I/O Power Supply
J2.A4	VDDIO_BANK47	FPGA.VCCO_47	J13 H15	Bank 47	S	1.8V / User defined	Bank47 I/O Power Supply
J2.A5	DGND	DGND	-	-	G	-	Digital ground
J2.A6	DGND	DGND	-	-	G	-	Digital ground
J2.A7	DGND	DGND	-	-	G	-	Digital ground
J2.A8	MGTREFCLK0P_128	FPGA.MGTREFCLK0P_128	F25	0V85	D
J2.A9	MGTREFCLK0N_128	FPGA.MGTREFCLK0N_128	F26	0V85	D
J2.A10	DGND	DGND	-	-	G	-	Digital ground
J2.A11	MGTHTXP0_128	FPGA.MGTHTXP0_128	G27	0V85	D
J2.A12	MGTHTXN0_128	FPGA.MGTHTXN0_128	G28	0V85	D
J2.A13	DGND	DGND	-	-	G	-	Digital ground
J2.A14	MGTHTXP2_128	FPGA.MGTHTXP2_128	C27	0V85	D
J2.A15	MGTHTXN2_128	FPGA.MGTHTXN2_128	C28	0V85	D
J2.A16	DGND	DGND	-	-	G	-	Digital ground
J2.A17	MGTHRXP0_128	FPGA.MGTHRXP0_128	H29	0V85	D
J2.A18	MGTHRXN0_128	FPGA.MGTHRXN0_128	H30	0V85	D
J2.A19	DGND	DGND	-	-	G	-	Digital ground
J2.A20	MGTHRXP2_128	FPGA.MGTHRXP2_128	D29	0V85	D
J2.A21	MGTHRXN2_128	FPGA.MGTHRXN2_128	D30	0V85	D
J2.A22	DGND	DGND	-	-	G	-	Digital ground
J2.A23	DGND	DGND	-	-	G	-	Digital ground
J2.A24	IO_L3P_AD9P_47	FPGA.IO_L3P_AD9P_47	B13	Bank 47	I/O	1.8V / User defined
J2.A25	IO_L3N_AD9N_47	FPGA.IO_L3N_AD9N_47	A13	Bank 47	I/O	1.8V / User defined
J2.A26	DGND	DGND	-	-	G	-	Digital ground
J2.A27	IO_L2P_AD10P_47	FPGA.IO_L2P_AD10P_47	B14	Bank 47	I/O	1.8V / User defined
J2.A28	IO_L2N_AD10N_47	FPGA.IO_L2N_AD10N_47	A14	Bank 47	I/O	1.8V / User defined
J2.A29	DGND	DGND	-	-	G	-	Digital ground
J2.A30	IO_L4P_AD8P_47	FPGA.IO_L4P_AD8P_47	C14	Bank 47	I/O	1.8V / User defined
J2.A31	IO_L4N_AD8N_47	FPGA.IO_L4P_AD8N_47	C13	Bank 47	I/O	1.8V / User defined
J2.A32	DGND	DGND	-	-	G	-	Digital ground
J2.A33	IO_L5P_HDGC_AD7P_47	FPGA.IO_L5P_HDGC_AD7P_47	D15	Bank 47	I/O	1.8V / User defined
J2.A34	IO_L5N_HDGC_AD7N_47	FPGA.IO_L5N_HDGC_AD7N_47	D14	Bank 47	I/O	1.8V / User defined
J2.A35	DGND	DGND	-	-	G	-	Digital ground
J2.A36	IO_L6P_HDGC_AD6P_47	FPGA.IO_L6P_HDGC_AD6P_47	E14	Bank 47	I/O	1.8V / User defined
J2.A37	IO_L6N_HDGC_AD6N_47	FPGA.IO_L6N_HDGC_AD6N_47	E13	Bank 47	I/O	1.8V / User defined
J2.A38	DGND	DGND	-	-	G	-	Digital ground
J2.A39	IO_L8P_HDGC_AD4P_47	FPGA.IO_L8P_HDGC_AD4P_47	G13	Bank 47	I/O	1.8V / User defined
J2.A40	IO_L8N_HDGC_AD4N_47	FPGA.IO_L8N_HDGC_AD4N_47	F13	Bank 47	I/O	1.8V / User defined
J2.A41	DGND	DGND	-	-	G	-	Digital ground
J2.A42	IO_L12P_AD0P_47	FPGA.IO_L12P_AD0P_47	H14	Bank 47	I/O	1.8V / User defined
J2.A43	IO_L12N_AD0N_47	FPGA.IO_L12N_AD0N_47	H13	Bank 47	I/O	1.8V / User defined
J2.A44	DGND	DGND	-	-	G	-	Digital ground
J2.A45	IO_L11P_AD1P_47	FPGA.IO_L11P_AD1P_47	K14	Bank 47	I/O	1.8V / User defined
J2.A46	IO_L11N_AD1N_47	FPGA.IO_L11N_AD1N_47	J14	Bank 47	I/O	1.8V / User defined
J2.A47	DGND	DGND	-	-	G	-	Digital ground
J2.A48	IO_L10P_AD2P_47	FPGA.IO_L10P_AD2P_47	K15	Bank 47	I/O	1.8V / User defined
J2.A49	IO_L10N_AD2N_47	FPGA.IO_L10N_AD2N_47	J15	Bank 47	I/O	1.8V / User defined
J2.A50	DGND	DGND	-	-	G	-	Digital ground
J2.A51	IO_L9P_AD3P_47	FPGA.IO_L9P_AD3P_47	G15	Bank 47	I/O	1.8V / User defined
J2.A52	IO_L9N_AD3N_47	FPGA.IO_L9N_AD3N_47	G14	Bank 47	I/O	1.8V / User defined
J2.A53	DGND	DGND	-	-	G	-	Digital ground
J2.A54	IO_L7P_HDGC_AD5P_47	FPGA.IO_L7P_HDGC_AD5P_47	F15	Bank 47	I/O	1.8V / User defined
J2.A55	IO_L7N_HDGC_AD5N_47	FPGA.IO_L7N_HDGC_AD5N_47	E15	Bank 47	I/O	1.8V / User defined
J2.A56	DGND	DGND	-	-	G	-	Digital ground
J2.A57	IO_L1P_AD11P_47	FPGA.IO_L1P_AD11P_47	B15	Bank 47	I/O	1.8V / User defined
J2.A58	IO_L1P_AD11N_47	FPGA.IO_L1P_AD11N_47	A15	Bank 47	I/O	1.8V / User defined
J2.A59	DGND	DGND	-	-	G	-	Digital ground
J2.A60	DGND	DGND	-	-	G	-	Digital ground

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J2.B1	VDDIO_BANK48	FPGA.VCCO_48	K11 H10	Bank 48	S	1.8V / User defined	Bank48 I/O Power Supply
J2.B2	VDDIO_BANK48	FPGA.VCCO_48	K11 H10	Bank 48	S	1.8V / User defined	Bank48 I/O Power Supply
J2.B3	VDDIO_BANK48	FPGA.VCCO_48	K11 H10	Bank 48	S	1.8V / User defined	Bank48 I/O Power Supply
J2.B4	VDDIO_BANK48	FPGA.VCCO_48	K11 H10	Bank 48	S	1.8V / User defined	Bank48 I/O Power Supply
J2.B5	DGND	DGND	-	-	G	-	Digital ground
J2.B6	DGND	DGND	-	-	G	-	Digital ground
J2.B7	DGND	DGND	-	-	G	-	Digital ground
J2.B8	DGND	DGND	-	-	G	-	Digital ground
J2.B9	MGTREFCLK1P_128	FPGA.MGTREFCLK1P_128	D25	0V85	D
J2.B10	MGTREFCLK1N_128	FPGA.MGTREFCLK1N_128	D26	0V85	D
J2.B11	DGND	DGND	-	-	G	-	Digital ground
J2.B12	MGTHTXP1_128	FPGA.MGTHTXP1_128	E27	0V85	D
J2.B13	MGTHTXN1_128	FPGA.MGTHTXN1_128	E28	0V85	D
J2.B14	DGND	DGND	-	-	G	-	Digital ground
J2.B15	MGTHRXP3_128	FPGA.MGTHRXP3_128	A27	0V85	D
J2.B16	MGTHRXN3_128	FPGA.MGTHRXN3_128	A28	0V85	D
J2.B17	DGND	DGND	-	-	G	-	Digital ground
J2.B18	MGTHRXP1_128	FPGA.MGTHRXP1_128	F29	0V85	D
J2.B19	MGTHRXN1_128	FPGA.MGTHRXN1_128	F30	0V85	D
J2.B20	DGND	DGND	-	-	G	-	Digital ground
J2.B21	MGTHRXP3_128	FPGA.MGTHRXP3_128	B29	0V85	D
J2.B22	MGTHRXN3_128	FPGA.MGTHRXN3_128	B30	0V85	D
J2.B23	DGND	DGND	-	-	G	-	Digital ground
J2.B24	DGND	DGND	-	-	G	-	Digital ground
J2.B25	IO_L3P_AD13P_48	FPGA.IO_L3P_AD13P_48	B10	Bank 48	I/O	1.8V / User defined
J2.B26	IO_L3N_AD13N_48	FPGA.IO_L3N_AD13N_48	A10	Bank 48	I/O	1.8V / User defined
J2.B27	DGND	DGND	-	-	G	-	Digital ground
J2.B28	IO_L6P_HDGC_48	FPGA.IO_L6P_HDGC_48	E10	Bank 48	I/O	1.8V / User defined
J2.B29	IO_L6N_HDGC_48	FPGA.IO_L6N_HDGC_48	D10	Bank 48	I/O	1.8V / User defined
J2.B30	DGND	DGND	-	-	G	-	Digital ground
J2.B31	IO_L8P_HDGC_48	FPGA.IO_L8P_HDGC_48	G10	Bank 48	I/O	1.8V / User defined
J2.B32	IO_L8N_HDGC_48	FPGA.IO_L8N_HDGC_48	F10	Bank 48	I/O	1.8V / User defined
J2.B33	DGND	DGND	-	-	G	-	Digital ground
J2.B34	IO_L10P_AD10P_48	FPGA.IO_L10P_AD10P_48	H12	Bank 48	I/O	1.8V / User defined
J2.B35	IO_L10N_AD10N_48	FPGA.IO_L10N_AD10N_48	G11	Bank 48	I/O	1.8V / User defined
J2.B36	DGND	DGND	-	-	G	-	Digital ground
J2.B37	IO_L12P_AD8P_48	FPGA.IO_L12P_AD8P_48	J11	Bank 48	I/O	1.8V / User defined
J2.B38	IO_L12N_AD8N_48	FPGA.IO_L12N_AD8N_48	J10	Bank 48	I/O	1.8V / User defined
J2.B39	DGND	DGND	-	-	G	-	Digital ground
J2.B40	IO_L11P_AD9P_48	FPGA.IO_L11P_AD9P_48	J12	Bank 48	I/O	1.8V / User defined
J2.B41	IO_L11N_AD9N_48	FPGA.IO_L11N_AD9N_48	H11	Bank 48	I/O	1.8V / User defined
J2.B42	DGND	DGND	-	-	G	-	Digital ground
J2.B43	IO_L9P_AD1P_48	FPGA.IO_L9P_AD11P_48	K13	Bank 48	I/O	1.8V / User defined
J2.B44	IO_L9N_AD1N_48	FPGA.IO_L9N_AD11N_48	K12	Bank 48	I/O	1.8V / User defined
J2.B45	DGND	DGND	-	-	G	-	Digital ground
J2.B46	IO_L7P_HDGC_48	FPGA.IO_L8P_HDGC_48	F11	Bank 48	I/O	1.8V / User defined
J2.B47	IO_L7N_HDGC_48	FPGA.IO_L8N_HDGC_48	G10	Bank 48	I/O	1.8V / User defined
J2.B48	DGND	DGND	-	-	G	-	Digital ground
J2.B49	IO_L5P_HDGC_48	FPGA.IO_L5P_HDGC_48	E12	Bank 48	I/O	1.8V / User defined
J2.B50	IO_L5N_HDGC_48	FPGA.IO_L5N_HDGC_48	D12	Bank 48	I/O	1.8V / User defined
J2.B51	DGND	DGND	-	-	G	-	Digital ground
J2.B52	IO_L4P_AD12P_48	FPGA.IO_L4P_AD12P_48	D11	Bank 48	I/O	1.8V / User defined
J2.B53	IO_L4N_AD12N_48	FPGA.IO_L4N_AD12N_48	C11	Bank 48	I/O	1.8V / User defined
J2.B54	DGND	DGND	-	-	G	-	Digital ground
J2.B55	IO_L1P_AD15P_48	FPGA.IO_L1P_AD15P_48	C12	Bank 48	I/O	1.8V / User defined
J2.B56	IO_L1N_AD15N_48	FPGA.IO_L1N_AD15N_48	B11	Bank 48	I/O	1.8V / User defined
J2.B57	DGND	DGND	-	-	G	-	Digital ground
J2.B58	IO_L2P_AD14P_48	FPGA.IO_L2P_AD14P_48	A12	Bank 48	I/O	1.8V / User defined
J2.B59	IO_L2P_AD14N_48	FPGA.IO_L2P_AD14N_48	A11	Bank 48	I/O	1.8V / User defined
J2.B60	DGND	DGND	-	-	G	-	Digital ground

SOM J2B pins (C1 to C60 - D1 to D60) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J2.C1	VDDIO_BANK66	FPGA.VCCO_66	Y6 W8 V5	Bank 66	S	User defined	BANK66 I/O Power Supply
J2.C2	VDDIO_BANK66	FPGA.VCCO_66	Y6 W8 V5	Bank 66	S	User defined	BANK66 I/O Power Supply
J2.C3	VDDIO_BANK66	FPGA.VCCO_66	Y6 W8 V5	Bank 66	S	User defined	BANK66 I/O Power Supply
J2.C4	DGND	DGND	-	-	G	-	Digital ground
J2.C5	MGTREFCLK0P_228	FPGA.MGTREFCLK0P_228	R8	0V85	D
J2.C6	MGTREFCLK0N_228	FPGA.MGTREFCLK0N_228	R7	0V85	D
J2.C7	DGND	DGND	-	-	G	-	Digital ground
J2.C8	MGTHTXP0_228	FPGA.MGTHTXP0_228	P6	0V85	D
J2.C9	MGTHTXN0_228	FPGA.MGTHTXN0_228	P5	0V85	D
J2.C10	DGND	DGND	-	-	G	-	Digital ground
J2.C11	MGTHTXP2_228	FPGA.MGTHTXP2_228	M6	0V85	D
J2.C12	MGTHTXN2_228	FPGA.MGTHTXN2_228	M5	0V85	D
J2.C13	DGND	DGND	-	-	G	-	Digital ground
J2.C14	MGTHRXP0_228	FPGA.MGTHRXP0_228	R4	0V85	D
J2.C15	MGTHRXN0_228	FPGA.MGTHRXN0_228	R3	0V85	D
J2.C16	DGND	DGND	-	-	G	-	Digital ground
J2.C17	MGTHRXP2_228	FPGA.MGTHRXP2_228	M2	0V85	D
J2.C18	MGTHRXN2_228	FPGA.MGTHRXN2_228	M1	0V85	D
J2.C19	DGND	DGND	-	-	G	-	Digital ground
J2.C20	DGND	DGND	-	-	G	-	Digital ground
J2.C21	IO_L6P_T0U_N10_AD6P_66	FPGA.IO_L6P_T0U_N10_AD6P_66	T1	Bank 66	I/O	User defined
J2.C22	IO_L6N_T0U_N11_AD6N_66	FPGA.IO_L6N_T0U_N11_AD6N_66	U1	Bank 66	I/O	User defined
J2.C23	DGND	DGND	-	-	G	-	Digital ground
J2.C24	IO_L5P_T0U_N8_AD14P_66	FPGA.IO_L5P_T0U_N8_AD14P_66	U2	Bank 66	I/O	User defined
J2.C25	IO_L5N_T0U_N9_AD14N_66	FPGA.IO_L5N_T0U_N9_AD14N_66	U3	Bank 66	I/O	User defined
J2.C26	DGND	DGND	-	-	G	-	Digital ground
J2.C27	IO_L4P_T0U_N6_DBC_AD7P_66	FPGA.IO_L4P_T0U_N6_DBC_AD7P_66	V2	Bank 66	I/O	User defined
J2.C28	IO_L4N_T0U_N7_DBC_AD7N_66	FPGA.IO_L4N_T0U_N7_DBC_AD7N_66	V1	Bank 66	I/O	User defined
J2.C29	DGND	DGND	-	-	G	-	Digital ground
J2.C30	IO_L3P_T0L_N4_AD15P_66	FPGA.IO_L3P_T0L_N4_AD15P_66	W2	Bank 66	I/O	User defined
J2.C30	IO_L3N_T0L_N5_AD15N_66	FPGA.IO_L3N_T0L_N5_AD15N_66	W1	Bank 66	I/O	User defined
J2.C32	DGND	DGND	-	-	G	-	Digital ground
J2.C33	IO_L2P_T0L_N2_66	FPGA.IO_L2P_T0L_N2_66	Y2	Bank 66	I/O	User defined
J2.C34	IO_L2N_T0L_N3_66	FPGA.IO_L2N_T0L_N3_66	Y1	Bank 66	I/O	User defined
J2.C35	DGND	DGND	-	-	G	-	Digital ground
J2.C36	IO_L1P_T0L_N0_DBC_66	FPGA.IO_L1P_T0L_N0_DBC_66	Y4	Bank 66	I/O	User defined
J2.C37	IO_L1N_T0L_N1_DBC_66	FPGA.IO_L1N_T0L_N1_DBC_66	Y3	Bank 66	I/O	User defined
J2.C38	DGND	DGND	-	-	G	-	Digital ground
J2.C39	IO_T0U_N12_VRP_66	FPGA.IO_T0U_N12_VRP_66	V3	Bank 66	I/O	User defined
J2.C40	DGND	DGND	-	-	G	-	Digital ground
J2.C41	IO_L13P_T2L_N0_GC_QBC_66	FPGA.IO_L13P_T2L_N0_GC_QBC_66	U8	Bank 66	I/O	User defined
J2.C42	IO_L13N_T2L_N1_GC_QBC_66	FPGA.IO_L13N_T2L_N1_GC_QBC_66	V8	Bank 66	I/O	User defined
J2.C43	DGND	DGND	-	-	G	-	Digital ground
J2.C44	IO_L18P_T2U_N10_AD2P_66	FPGA.IO_L18P_T2U_N10_AD2P_66	T11	Bank 66	I/O	User defined
J2.C45	IO_L18N_T2U_N11_AD2N_66	FPGA.IO_L18N_T2U_N11_AD2N_66	U10	Bank 66	I/O	User defined
J2.C46	DGND	DGND	-	-	G	-	Digital ground
J2.C47	IO_L16P_T2U_N6_QBC_AD3P_66	FPGA.IO_L16P_T2U_N6_QBC_AD3P_66	W11	Bank 66	I/O	User defined
J2.C48	IO_L16N_T2U_N7_QBC_AD3N_66	FPGA.IO_L16N_T2U_N7_QBC_AD3N_66	W10	Bank 66	I/O	User defined
J2.C49	DGND	DGND	-	-	G	-	Digital ground
J2.C50	IO_L15P_T2L_N4_AD11P_66	FPGA.IO_L15P_T2L_N4_AD11P_66	U11	Bank 66	I/O	User defined
J2.C51	IO_L15N_T2L_N5_AD11N_66	FPGA.IO_L15N_T2L_N5_AD11N_66	V11	Bank 66	I/O	User defined
J2.C52	DGND	DGND	-	-	G	-	Digital ground
J2.C53	IO_L17P_T2U_N8_AD10P_66	FPGA.IO_L17P_T2U_N8_AD10P_66	U9	Bank 66	I/O	User defined
J2.C54	IO_L17N_T2U_N9_AD10N_66	FPGA.IO_L17N_T2U_N9_AD10N_66	V9	Bank 66	I/O	User defined
J2.C55	DGND	DGND	-	-	G	-	Digital ground
J2.C56	IO_L14P_T2L_N2_GC_66	FPGA.IO_L14P_T2L_N2_GC_66	Y9	Bank 66	I/O	User defined
J2.C57	IO_L14N_T2L_N3_GC_66	FPGA.IO_L14N_T2L_N3_GC_66	Y8	Bank 66	I/O	User defined
J2.C58	DGND	DGND	-	-	G	-	Digital ground
J2.C59	IO_T2U_N12_66	FPGA.IO_T2U_N12_66	Y10	Bank 66	I/O	User defined
J2.C60	DGND	DGND	-	-	G	-	Digital ground

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J2.D1	VDDIO_BANK66	FPGA.VCCO_66	Y6 W8 V5	Bank 66	S	User defined	BANK66 I/O Power Supply
J2.D2	VDDIO_BANK66	FPGA.VCCO_66	Y6 W8 V5	Bank 66	S	User defined	BANK66 I/O Power Supply
J2.D3	VDDIO_BANK66	FPGA.VCCO_66	Y6 W8 V5	Bank 66	S	User defined	BANK66 I/O Power Supply
J2.D4	VREF66	FPGA.VREF66	W9	Bank 66	S	User defined	BANK66 I/O VREF
J2.D5	DGND	DGND	-	-	G	-	Digital ground
J2.D6	MGTREFCLK1P_228	FPGA.MGTREFCLK1P_228	N8	0V85	D
J2.D7	MGTREFCLK1N_228	FPGA.MGTREFCLK1N_228	N7	0V85	D
J2.D8	DGND	DGND	-	-	G	-	Digital ground
J2.D9	MGTHTXP1_228	FPGA.MGTHTXP0_228	N4	0V85	D
J2.D10	MGTHTXN1_228	FPGA.MGTHTXN0_228	N3	0V85	D
J2.D11	DGND	DGND	-	-	G	-	Digital ground
J2.D12	MGTHTXP3_228	FPGA.MGTHTXP3_228	K6	0V85	D
J2.D13	MGTHTXN3_228	FPGA.MGTHTXN3_228	K5	0V85	D
J2.D14	DGND	DGND	-	-	G	-	Digital ground
J2.D15	MGTHRXP1_228	FPGA.MGTHRXP1_228	P2	0V85	D
J2.D16	MGTHRXN1_228	FPGA.MGTHRXN1_228	P1	0V85	D
J2.D17	DGND	DGND	-	-	G	-	Digital ground
J2.D18	MGTHRXP3_228	FPGA.MGTHRXP3_228	L4	0V85	D
J2.D19	MGTHRXN3_228	FPGA.MGTHRXN3_228	L3	0V85	D
J2.D20	DGND	DGND	-	-	G	-	Digital ground
J2.D21	DGND	DGND	-	-	G	-	Digital ground
J2.D22	IO_L10P_T1U_N6_QBC_AD4P_66	FPGA.IO_L10P_T1U_N6_QBC_AD4P_66	U7	Bank 66	I/O	User defined
J2.D23	IO_L10N_T1U_N7_QBC_AD4N_66	FPGA.IO_L10N_T1U_N7_QBC_AD4N_66	U6	Bank 66	I/O	User defined
J2.D24	DGND	DGND	-	-	G	-	Digital ground
J2.D25	IO_L8P_T1L_N2_AD5P_66	FPGA.IO_L8P_T1L_N2_AD5P_66	V4	Bank 66	I/O	User defined
J2.D26	IO_L8N_T1L_N3_AD5N_66	FPGA.IO_L8N_T1L_N3_AD5N_66	W4	Bank 66	I/O	User defined
J2.D27	DGND	DGND	-	-	G	-	Digital ground
J2.D28	IO_L7P_T1L_N0_QBC_AD13P_66	FPGA.IO_L7P_T1L_N0_QBC_AD13P_66	W5	Bank 66	I/O	User defined
J2.D29	IO_L7N_T1L_N1_QBC_AD13N_66	FPGA.IO_L7N_T1L_N1_QBC_AD13N_66	Y5	Bank 66	I/O	User defined
J2.D30	DGND	DGND	-	-	G	-	Digital ground
J2.D31	IO_L9P_T1L_N4_AD12P_66	FPGA.IO_L9P_T1L_N4_AD12P_66	U5	Bank 66	I/O	User defined
J2.D32	IO_L9N_T1L_N5_AD12N_66	FPGA.IO_L9N_T1L_N5_AD12N_66	U4	Bank 66	I/O	User defined
J2.D33	DGND	DGND	-	-	G	-	Digital ground
J2.D34	IO_L11P_T1U_N8_GC_66	FPGA.IO_L11P_T1U_N8_GC_66	V7	Bank 66	I/O	User defined
J2.D35	IO_L11N_T1U_N9_GC_66	FPGA.IO_L11N_T1U_N9_GC_66	V6	Bank 66	I/O	User defined
J2.D36	DGND	DGND	-	-	G	-	Digital ground
J2.D37	IO_L12P_T1U_N10_GC_66	FPGA.IO_L12P_T1U_N10_GC_66	W7	Bank 66	I/O	User defined
J2.D38	IO_L12N_T1U_N11_GC_66	FPGA.IO_L12N_T1U_N11_GC_66	W6	Bank 66	I/O	User defined
J2.D39	DGND	DGND	-	-	G	-	Digital ground
J2.D40	IO_T1U_N12_66	FPGA.IO_T1U_N12_66	Y7	Bank 66	I/O	User defined
J2.D41	DGND	DGND	-	-	G	-	Digital ground
J2.D42	IO_L23P_T3U_N8_66	FPGA.IO_L23P_T3U_N8_66	L12	Bank 66	I/O	User defined
J2.D43	IO_L23N_T3U_N9_66	FPGA.IO_L23N_T3U_N9_66	L11	Bank 66	I/O	User defined
J2.D44	DGND	DGND	-	-	G	-	Digital ground
J2.D45	IO_L24P_T3U_N10_66	FPGA.IO_L24P_T3U_N10_66	L10	Bank 66	I/O	User defined
J2.D46	IO_L24N_T3U_N11_66	FPGA.IO_L24N_T3U_N11_66	K10	Bank 66	I/O	User defined
J2.D47	DGND	DGND	-	-	G	-	Digital ground
J2.D48	IO_L19P_T3L_N0_DBC_AD9P_66	FPGA.IO_L19P_T3L_N0_DBC_AD9P_66	R10	Bank 66	I/O	User defined
J2.D49	IO_L19N_T3L_N1_DBC_AD9N_66	FPGA.IO_L19N_T3L_N1_DBC_AD9N_66	T10	Bank 66	I/O	User defined
J2.D50	DGND	DGND	-	-	G	-	Digital ground
J2.D51	IO_L21P_T3L_N4_AD8P_66	FPGA.IO_L21P_T3L_N4_AD8P_66	N12	Bank 66	I/O	User defined
J2.D52	IO_L21N_T3L_N5_AD8N_66	FPGA.IO_L21N_T3L_N5_AD8N_66	M12	Bank 66	I/O	User defined
J2.D53	DGND	DGND	-	-	G	-	Digital ground
J2.D54	IO_L22P_T3U_N6_DBC_AD0P_66	FPGA.IO_L22P_T3U_N6_DBC_AD0P_66	N10	Bank 66	I/O	User defined
J2.D55	IO_L22N_T3U_N7_DBC_AD0N_66	FPGA.IO_L22N_T3U_N7_DBC_AD0N_66	M10	Bank 66	I/O	User defined
J2.D56	DGND	DGND	-	-	G	-	Digital ground
J2.D57	IO_L20P_T3L_N2_AD1P_66	FPGA.IO_L20P_T3L_N2_AD1P_66	P11	Bank 66	I/O	User defined
J2.D58	IO_L20N_T3L_N3_AD1N_66	FPGA.IO_L20N_T3L_N3_AD1N_66	P10	Bank 66	I/O	User defined
J2.D59	DGND	DGND	-	-	G	-	Digital ground
J2.D60	IO_T3U_N12_66	FPGA.IO_T3U_N12_66	N11	Bank 66	I/O	User defined

SOM J3A pins (A1 to A60 - B1 to B60) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J3.A1	VDDIO_BANK65	FPGA.VCCO_65	AD8 AC5 AA9	Bank 65	S	User defined	Bank65 I/O Power Supply
J3.A2	VDDIO_BANK65	FPGA.VCCO_65	AD8 AC5 AA9	Bank 65	S	User defined	Bank65 I/O Power Supply
J3.A3	VDDIO_BANK65	FPGA.VCCO_65	AD8 AC5 AA9	Bank 65	S	User defined	Bank65 I/O Power Supply
J3.A4	DGND	DGND	-	-	G	-	Digital ground
J3.A5	MGTREFCLK0P_229	FPGA.MGTREFCLK0P_229	L8	0V85	D
J3.A6	MGTREFCLK0N_229	FPGA.MGTREFCLK0N_229	L7	0V85	D
J3.A7	DGND	DGND	-	-	G	-	Digital ground
J3.A8	MGTHTXP0_229	FPGA.MGTHTXP0_229	J4	0V85	D
J3.A9	MGTHTXN0_229	FPGA.MGTHTXN0_229	J3	0V85	D
J3.A10	DGND	DGND	-	-	G	-	Digital ground
J3.A11	MGTHTXP2_229	FPGA.MGTHTXP2_229	F6	0V85	D
J3.A12	MGTHTXN2_229	FPGA.MGTHTXN2_229	F5	0V85	D
J3.A13	DGND	DGND	-	-	G	-	Digital ground
J3.A14	MGTHRXP0_229	FPGA.MGTHRXP0_229	K2	0V85	D
J3.A15	MGTHRXN0_229	FPGA.MGTHRXN0_229	K1	0V85	D
J3.A16	DGND	DGND	-	-	G	-	Digital ground
J3.A17	MGTHRXP2_229	FPGA.MGTHRXP2_229	G4	0V85	D
J3.A18	MGTHRXN2_229	FPGA.MGTHRXN2_229	G3	0V85	D
J3.A19	DGND	DGND	-	-	G	-	Digital ground
J3.A20	DGND	DGND	-	-	G	-	Digital ground
J3.A21	IO_L2P_T0L_N2_65	FPGA.IO_L3P_T0L_N2_65	AE13	Bank 65	I/O	User defined
J3.A22	IO_L2N_T0L_N3_65	FPGA.IO_L2N_T0L_N3_65	AF13	Bank 65	I/O	User defined
J3.A23	DGND	DGND	-	-	G	-	Digital ground
J3.A24	IO_L1P_T0L_N0_DBC_66	FPGA.IO_L1P_T0L_N0_DBC_66	AB13	Bank 65	I/O	User defined
J3.A25	IO_L1N_T0L_N1_DBC_66	FPGA.IO_L1N_T0L_N1_DBC_66	AC13	Bank 65	I/O	User defined
J3.A26	DGND	DGND	-	-	G	-	Digital ground
J3.A27	IO_L5P_T0U_N8_AD14P_65	FPGA.IO_L5P_T0U_N8_AD14P_65	AA12	Bank 65	I/O	User defined
J3.A28	IO_L5N_T0U_N9_AD14N_65	FPGA.IO_L5N_T0U_N9_AD14N_65	AA11	Bank 65	I/O	User defined
J3.A29	DGND	DGND	-	-	G	-	Digital ground
J3.A30	IO_L6P_T0U_N10_AD6P_65	FPGA.IO_L6P_T0U_N10_AD6P_65	AB11	Bank 65	I/O	User defined
J3.A31	IO_L6N_T0U_N11_AD6N_65	FPGA.IO_L6N_T0U_N11_AD6N_65	AB10	Bank 65	I/O	User defined
J3.A32	DGND	DGND	-	-	G	-	Digital ground
J3.A33	IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65	FPGA.IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65	AC11	Bank 65	I/O	User defined
J3.A34	IO_L4N_T0U_N7_DBC_AD7N_65	FPGA.IO_L4N_T0U_N7_DBC_AD7N_65	AD11	Bank 65	I/O	User defined
J3.A35	DGND	DGND	-	-	G	-	Digital ground
J3.A36	IO_L3P_T0L_N4_AD15P_65	FPGA.IO_L3P_T0L_N4_AD15P_65	AD12	Bank 65	I/O	User defined
J3.A37	IO_L3N_T0L_N5_AD15N_65	FPGA.IO_L3N_T0L_N5_AD15N_65	AE12	Bank 65	I/O	User defined
J3.A38	DGND	DGND	-	-	G	-	Digital ground
J3.A39	IO_T0U_N12_VRP_65	FPGA.IO_T0U_N12_VRP_65	AC12	Bank 65	I/O	User defined
J3.A40	DGND	DGND	-	-	G	-	Digital ground
J3.A41	IO_L13P_T2L_N0_GC_QBC_65	FPGA.IO_L13P_T2L_N0_GC_QBC_65	AB6	Bank 65	I/O	User defined
J3.A42	IO_L13N_T2L_N1_GC_QBC_65	FPGA.IO_L13N_T2L_N1_GC_QBC_65	AB5	Bank 65	I/O	User defined
J3.A43	DGND	DGND	-	-	G	-	Digital ground
J3.A44	IO_L14P_T2L_N2_GC_65	FPGA.IO_L14P_T2L_N2_GC_65	AC6	Bank 65	I/O	User defined
J3.A45	IO_L14N_T2L_N3_GC_65	FPGA.IO_L14N_T2L_N3_GC_65	AD6	Bank 65	I/O	User defined
J3.A46	DGND	DGND	-	-	G	-	Digital ground
J3.A47	IO_L17P_T2U_N8_AD10P_65	FPGA.IO_L17P_T2U_N8_AD10P_65	AD4	Bank 65	I/O	User defined
J3.A48	IO_L17N_T2U_N9_AD10N_65	FPGA.IO_L17N_T2U_N9_AD10N_65	AE4	Bank 65	I/O	User defined
J3.A49	DGND	DGND	-	-	G	-	Digital ground
J3.A50	IO_L16P_T2U_N6_QBC_AD3P_65	FPGA.IO_L16P_T2U_N6_QBC_AD3P_65	AD5	Bank 65	I/O	User defined
J3.A51	IO_L16N_T2U_N7_QBC_AD3N_65	FPGA.IO_L16N_T2U_N7_QBC_AD3N_65	AE5	Bank 65	I/O	User defined
J3.A52	DGND	DGND	-	-	G	-	Digital ground
J3.A53	IO_L18P_T2U_N10_AD2P_65	FPGA.IO_L18P_T2U_N10_AD2P_65	AB4	Bank 65	I/O	User defined
J3.A54	IO_L18N_T2U_N11_AD2N_65	FPGA.IO_L18N_T2U_N11_AD2N_65	AC4	Bank 65	I/O	User defined
J3.A55	DGND	DGND	-	-	G	-	Digital ground
J3.A56	IO_L15P_T2L_N4_AD11P_65	FPGA.IO_L15P_T2L_N4_AD11P_65	AA6	Bank 65	I/O	User defined
J3.A57	IO_L15N_T2L_N5_AD11N_65	FPGA.IO_L15N_T2L_N5_AD11N_65	AA5	Bank 65	I/O	User defined
J3.A58	DGND	DGND	-	-	G	-	Digital ground
J3.A59	IO_T2U_N12_65	FPGA.IO_T2U_N12_65	AE7	Bank 65	I/O	User defined
J3.A60	DGND	DGND	-	-	G	-	Digital ground

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J3.B1	VDDIO_BANK65	FPGA.VCCO_65	AD8 AC5 AA9	Bank 65	S	User defined	Bank65 I/O Power Supply
J3.B2	VDDIO_BANK65	FPGA.VCCO_65	AD8 AC5 AA9	Bank 65	S	User defined	Bank65 I/O Power Supply
J3.B3	VDDIO_BANK65	FPGA.VCCO_65	AD8 AC5 AA9	Bank 65	S	User defined	Bank65 I/O Power Supply
J3.B4	VREF65	FPGA.VREF65	AA10	Bank 65	S	User defined	Bank65 VREF
J3.B5	DGND	DGND	-	-	G	-	Digital ground
J3.B6	MGTREFCLK1P_229	FPGA.MGTREFCLK1P_229	J8	0V85	D
J3.B7	MGTREFCLK1N_229	FPGA.MGTREFCLK1N_229	J7	0V85	D
J3.B8	DGND	DGND	-	-	G	-	Digital ground
J3.B9	MGTHTXP1_229	FPGA.MGTHTXP1_229	H6	0V85	D
J3.B10	MGTHTXN1_229	FPGA.MGTHTXN1_229	H5	0V85	D
J3.B11	DGND	DGND	-	-	G	-	Digital ground
J3.B12	MGTHRXP3_229	FPGA.MGTHRXP3_229	E4	0V85	D
J3.B13	MGTHRXN3_229	FPGA.MGTHRXN3_229	E3	0V85	D
J3.B14	DGND	DGND	-	-	G	-	Digital ground
J3.B15	MGTHRXP1_229	FPGA.MGTHRXP1_229	H2	0V85	D
J3.B16	MGTHRXN1_229	FPGA.MGTHRXN1_229	H1	0V85	D
J3.B17	DGND	DGND	-	-	G	-	Digital ground
J3.B18	MGTHRXP3_229	FPGA.MGTHRXP3_229	F2	0V85	D
J3.B19	MGTHRXN3_229	FPGA.MGTHRXN3_229	F1	0V85	D
J3.B20	DGND	DGND	-	-	G	-	Digital ground
J3.B21	DGND	DGND	-	-	G	-	Digital ground
J3.B22	IO_L8P_T1L_N2_AD5P_65	FPGA.IO_L8P_T1L_N2_AD5P_65	AD10	Bank 65	I/O	User defined
J3.B23	IO_L8N_T1L_N3_AD5N_65	FPGA.IO_L8N_T1L_N3_AD5N_65	AE10	Bank 65	I/O	User defined
J3.B24	DGND	DGND	-	-	G	-	Digital ground
J3.B25	IO_L10P_T1U_N6_QBC_AD4P_65	FPGA.IO_L10P_T1U_N6_QBC_AD4P_65	AA8	Bank 65	I/O	User defined
J3.B26	IO_L10N_T1U_N7_QBC_AD4N_65	FPGA.IO_L10N_T1U_N7_QBC_AD4N_65	AA7	Bank 65	I/O	User defined
J3.B27	DGND	DGND	-	-	G	-	Digital ground
J3.B28	IO_L7P_T1L_N0_QBC_AD13P_65	FPGA.IO_L7P_T1L_N0_QBC_AD13P_65	AB9	Bank 65	I/O	User defined
J3.B29	IO_L7N_T1L_N1_QBC_AD13N_65	FPGA.IO_L7N_T1L_N1_QBC_AD13N_65	AC9	Bank 65	I/O	User defined
J3.B30	DGND	DGND	-	-	G	-	Digital ground
J3.B31	IO_L12P_T1U_N10_GC_65	FPGA.IO_L12P_T1U_N10_GC_65	AB8	Bank 65	I/O	User defined
J3.B32	IO_L12N_T1U_N11_GC_65	FPGA.IO_L12N_T1U_N11_GC_65	AC8	Bank 65	I/O	User defined
J3.B33	DGND	DGND	-	-	G	-	Digital ground
J3.B34	IO_L11P_T1U_N8_GC_65	FPGA.IO_L11P_T1U_N8_GC_65	AB8	Bank 65	I/O	User defined
J3.B35	IO_L11N_T1U_N9_GC_65	FPGA.IO_L11N_T1U_N9_GC_65	AC8	Bank 65	I/O	User defined
J3.B36	DGND	DGND	-	-	G	-	Digital ground
J3.B37	IO_L9P_T1L_N4_AD12P_65	FPGA.IO_L9P_T1L_N4_AD12P_65	AD9	Bank 65	I/O	User defined
J3.B38	IO_L9N_T1L_N5_AD12N_65	FPGA.IO_L9N_T1L_N5_AD12N_65	AE9	Bank 65	I/O	User defined
J3.B39	DGND	DGND	-	-	G	-	Digital ground
J3.B40	IO_T1U_N12_65	FPGA.IO_T1U_N12_65	AE8	Bank 65	I/O	User defined
J3.B41	DGND	DGND	-	-	G	-	Digital ground
J3.B42	IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65	FPGA.IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65	AA1	Bank 65	I/O	User defined
J3.B43	IO_L24N_T3U_N11_PERSTN0_65	FPGA.IO_L24N_T3U_N11_PERSTN0_65	AB1	Bank 65	I/O	User defined
J3.B44	DGND	DGND	-	-	G	-	Digital ground
J3.B45	IO_L22P_T3U_N6_DBC_AD0P_65	FPGA.IO_L22P_T3U_N6_DBC_AD0P_65	AC1	Bank 65	I/O	User defined
J3.B46	IO_L22N_T3U_N7_DBC_AD0N_65	FPGA.IO_L22N_T3U_N7_DBC_AD0N_65	AD1	Bank 65	I/O	User defined
J3.B47	DGND	DGND	-	-	G	-	Digital ground
J3.B45	IO_L23P_T3U_N8_I2C_SCLK_65	FPGA.IO_L23P_T3U_N8_I2C_SCLK_65	AA3	Bank 65	I/O	User defined
J3.B46	IO_L23N_T3U_N9_65	FPGA.IO_L23N_T3U_N9_65	AA2	Bank 65	I/O	User defined
J3.B50	DGND	DGND	-	-	G	-	Digital ground
J3.B51	IO_L19P_T3L_N0_DBC_AD9P_65	FPGA.IO_L19P_T3L_N0_DBC_AD9P_65	AB3	Bank 65	I/O	User defined
J3.B52	IO_L19N_T3L_N1_DBC_AD9N_65	FPGA.IO_L19N_T3L_N1_DBC_AD9N_65	AC3	Bank 65	I/O	User defined
J3.B53	DGND	DGND	-	-	G	-	Digital ground
J3.B54	IO_L21P_T3L_N4_AD8P_65	FPGA.IO_L21P_T3L_N4_AD8P_65	AC2	Bank 65	I/O	User defined
J3.B55	IO_L21N_T3L_N5_AD8N_65	FPGA.IO_L21N_T3L_N5_AD8N_65	AD2	Bank 65	I/O	User defined
J3.B56	DGND	DGND	-	-	G	-	Digital ground
J3.B57	IO_L20P_T3L_N2_AD1P_65	FPGA.IO_L20P_T3L_N2_AD1P_65	AC2	Bank 65	I/O	User defined
J3.B58	IO_L20N_T3L_N3_AD1N_65	FPGA.IO_L20N_T3L_N3_AD1N_65	AD2	Bank 65	I/O	User defined
J3.B59	DGND	DGND	-	-	G	-	Digital ground
J3.B60	IO_T3U_N12_65	FPGA.IO_T3U_N12_65	AE1	Bank 65	I/O	User defined

SOM J3B pins (C1 to C60 - D1 to D60) declaration

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J3.C1	VDDIO_BANK64	FPGA.VCCO_64	AH10 AG12 AF9	Bank 64	S	User defined	Bank64 I/O Power Supply
J3.C2	VDDIO_BANK64	FPGA.VCCO_64	AH10 AG12 AF9	Bank 64	S	User defined	Bank64 I/O Power Supply
J3.C3	VDDIO_BANK64	FPGA.VCCO_64	AH10 AG12 AF9	Bank 64	S	User defined	Bank64 I/O Power Supply
J3.C4	DGND	DGND	-	-	G	-	Digital ground
J3.C5	MGTREFCLK0P_230	FPGA.MGTREFCLK0P_230	G8	0V85	D
J3.C6	MGTREFCLK0N_230	FPGA.MGTREFCLK0N_230	G7	0V85	D
J3.C7	DGND	DGND	-	-	G	-	Digital ground
J3.C8	MGTHTXP0_230	FPGA.MGTHTXP0_230	D6	0V85	D
J3.C9	MGTHTXN0_230	FPGA.MGTHTXN0_230	D5	0V85	D
J3.C10	DGND	DGND	-	-	G	-	Digital ground
J3.C11	MGTHTXP2_230	FPGA.MGTHTXP2_230	B6	0V85	D
J3.C12	MGTHTXN2_230	FPGA.MGTHTXN2_230	B5	0V85	D
J3.C13	DGND	DGND	-	-	G	-	Digital ground
J3.C14	MGTHRXP0_230	FPGA.MGTHRXP0_230	D2	0V85	D
J3.C15	MGTHRXN0_230	FPGA.MGTHRXN0_230	D1	0V85	D
J3.C16	DGND	DGND	-	-	G	-	Digital ground
J3.C17	MGTHRXP2_230	FPGA.MGTHRXP2_230	B2	0V85	D
J3.C18	MGTHRXN2_230	FPGA.MGTHRXN2_230	B1	0V85	D
J3.C19	DGND	DGND	-	-	G	-	Digital ground
J3.C20	DGND	DGND	-	-	G	-	Digital ground
J3.C21	IO_L5P_T0U_N8_AD14P_64	FPGA.IO_L5P_T0U_N8_AD14P_64	AJ11	Bank 64	I/O	User defined
J3.C22	IO_L5N_T0U_N8_AD14P_64	FPGA.IO_L5N_T0U_N8_AD14N_64	AK11	Bank 64	I/O	User defined
J3.C23	DGND	DGND	-	-	G	-	Digital ground
J3.C24	IO_L1P_T0L_N0_DBC_64	FPGA.IO_L1P_T0L_N0_DBC_64	AF11	Bank 64	I/O	User defined
J3.C25	IO_L1N_T0L_N1_DBC_64	FPGA.IO_L1N_T0L_N1_DBC_64	AG11	Bank 64	I/O	User defined
J3.C26	DGND	DGND	-	-	G	-	Digital ground
J3.C27	IO_L3P_T0L_N4_AD15P_64	FPGA.IO_L3P_T0L_N4_AD15P_64	AH12	Bank 64	I/O	User defined
J3.C28	IO_L3N_T0L_N5_AD15N_64	FPGA.IO_L3N_T0L_N5_AD15N_64	AJ12	Bank 64	I/O	User defined
J3.C29	DGND	DGND	-	-	G	-	Digital ground
J3.C30	IO_L2P_T0L_N2_64	FPGA.IO_L2P_T0L_N2_64	AG13	Bank 64	I/O	User defined
J3.C31	IO_L2N_T0L_N3_64	FPGA.IO_L2N_T0L_N3_64	AH13	Bank 64	I/O	User defined
J3.C32	DGND	DGND	-	-	G	-	Digital ground
J3.C33	IO_L6P_T0U_N10_AD6P_64	FPGA.IO_L6P_T0U_N10_AD6P_64	AJ10	Bank 64	I/O	User defined
J3.C34	IO_L6N_T0U_N11_AD6N_64	FPGA.IO_L6N_T0U_N11_AD6N_64	AK10	Bank 64	I/O	User defined
J3.C35	DGND	DGND	-	-	G	-	Digital ground
J3.C36	IO_L4P_T0U_N6_DBC_AD7P_64	FPGA.IO_L4P_T0U_N6_DBC_AD7P_64	AK13	Bank 64	I/O	User defined
J3.C37	IO_L4N_T0U_N7_DBC_AD7N_64	FPGA.IO_L4N_T0U_N7_DBC_AD7N_64	AK12	Bank 64	I/O	User defined
J3.C38	DGND	DGND	-	-	G	-	Digital ground
J3.C39	IO_T0U_N12_VRP_64	FPGA.IO_T0U_N12_VRP_64	AH11	Bank 64	I/O	User defined
J3.C40	DGND	DGND	-	-	G	-	Digital ground
J3.C41	IO_L16P_T2U_N6_QBC_AD3P_64	FPGA.IO_L16P_T2U_N6_QBC_AD3P_64	AF6	Bank 64	I/O	User defined
J3.C42	IO_L16N_T2U_N7_QBC_AD3N_64	FPGA.IO_L16N_T2U_N7_QBC_AD3N_64	AF5	Bank 64	I/O	User defined
J3.C43	DGND	DGND	-	-	G	-	Digital ground
J3.C44	IO_L13P_T2L_N0_GC_QBC_64	FPGA.IO_L13P_T2L_N0_GC_QBC_64	AG6	Bank 64	I/O	User defined
J3.C45	IO_L13N_T2L_N1_GC_QBC_64	FPGA.IO_L13N_T2L_N1_GC_QBC_64	AG5	Bank 64	I/O	User defined
J3.C46	DGND	DGND	-	-	G	-	Digital ground
J3.C47	IO_L15P_T2L_N4_AD11P_64	FPGA.IO_L15P_T2L_N4_AD11P_64	AK7	Bank 64	I/O	User defined
J3.C48	IO_L15N_T2L_N5_AD11N_64	FPGA.IO_L15N_T2L_N5_AD11N_64	AK6	Bank 64	I/O	User defined
J3.C49	DGND	DGND	-	-	G	-	Digital ground
J3.C50	IO_L17P_T2U_N8_AD10P_64	FPGA.IO_L17P_T2U_N8_AD10P_64	AJ5	Bank 64	I/O	User defined
J3.C51	IO_L17N_T2U_N9_AD10N_64	FPGA.IO_L17N_T2U_N9_AD10N_64	AK5	Bank 64	I/O	User defined
J3.C52	DGND	DGND	-	-	G	-	Digital ground
J3.C53	IO_L14P_T2L_N2_GC_64	FPGA.IO_L14P_T2L_N2_GC_64	AH6	Bank 64	I/O	User defined
J3.C54	IO_L14N_T2L_N3_GC_64	FPGA.IO_L14N_T2L_N3_GC_64	AJ6	Bank 64	I/O	User defined
J3.C55	DGND	DGND	-	-	G	-	Digital ground
J3.C56	IO_L18P_T2U_N10_AD2P_64	FPGA.IO_L18P_T2U_N10_AD2P_64	AH4	Bank 64	I/O	User defined
J3.C57	IO_L18N_T2U_N11_AD2N_64	FPGA.IO_L18N_T2U_N11_AD2N_64	AJ4	Bank 64	I/O	User defined
J3.C58	DGND	DGND	-	-	G	-	Digital ground
J3.C59	IO_T2U_N12_64	FPGA.IO_T2U_N12_64	AG4	Bank 64	I/O	User defined
J3.C60	DGND	DGND	-	-	G	-	Digital ground

Pin	Pin Name	Internal Connections	Ball/pin #	Supply Group	Type	Voltage	Note
J3.D1	VDDIO_BANK64	FPGA.VCCO_64	AH10 AG12 AF9	Bank 64	S	User defined	Bank64 I/O Power Supply
J3.D2	VDDIO_BANK64	FPGA.VCCO_64	AH10 AG12 AF9	Bank 64	S	User defined	Bank64 I/O Power Supply
J3.D3	VDDIO_BANK64	FPGA.VCCO_64	AH10 AG12 AF9	Bank 64	S	User defined	Bank64 I/O Power Supply
J3.D4	VREF64	FPGA.VREF64	AF12	Bank 64	S	User defined	Bank64 VREF
J3.D5	DGND	DGND	-	-	G	-	Digital ground
J3.B6	MGTREFCLK1P_230	FPGA.MGTREFCLK1P_230	E8	0V85	D
J3.B7	MGTREFCLK1N_230	FPGA.MGTREFCLK1N_230	E7	0V85	D
J3.D8	DGND	DGND	-	-	G	-	Digital ground
J3.B9	MGTHTXP1_230	FPGA.MGTHTXP1_230	C8	0V85	D
J3.B10	MGTHTXN1_230	FPGA.MGTHTXN1_230	C7	0V85	D
J3.D11	DGND	DGND	-	-	G	-	Digital ground
J3.B12	MGTHRXP3_230	FPGA.MGTHRXP3_230	A8	0V85	D
J3.B13	MGTHRXN3_230	FPGA.MGTHRXN3_230	A7	0V85	D
J3.D14	DGND	DGND	-	-	G	-	Digital ground
J3.B15	MGTHRXP1_230	FPGA.MGTHRXP1_230	C4	0V85	D
J3.B16	MGTHRXN1_230	FPGA.MGTHRXN1_230	C3	0V85	D
J3.D17	DGND	DGND	-	-	G	-	Digital ground
J3.B18	MGTHRXP3_230	FPGA.MGTHRXP3_230	A4	0V85	D
J3.B19	MGTHRXN3_230	FPGA.MGTHRXN3_230	A3	0V85	D
J3.D20	DGND	DGND	-	-	G	-	Digital ground
J3.D21	DGND	DGND	-	-	G	-	Digital ground
J3.D22	IO_L8P_T1L_N2_AD5P_64	FPGA.IO_L8P_T1L_N2_AD5P_64	AF10	Bank 64	I/O	User defined
J3.D23	IO_L8N_T1L_N3_AD5N_64	FPGA.IO_L8N_T1L_N3_AD5N_64	AG10	Bank 64	I/O	User defined
J3.D24	DGND	DGND	-	-	G	-	Digital ground
J3.D25	IO_L7P_T1L_N0_QBC_AD13P_64	FPGA.IO_L7P_T1L_N0_QBC_AD13P_64	AF8	Bank 64	I/O	User defined
J3.D26	IO_L7N_T1L_N1_QBC_AD13N_64	FPGA.IO_L7N_T1L_N1_QBC_AD13N_64	AF7	Bank 64	I/O	User defined
J3.D27	DGND	DGND	-	-	G	-	Digital ground
J3.D28	IO_L12P_T1U_N10_GC_64	FPGA.IO_L12P_T1U_N10_GC_64	AG8	Bank 64	I/O	User defined
J3.D29	IO_L12N_T1U_N11_GC_64	FPGA.IO_L12N_T1U_N11_GC_64	AH8	Bank 64	I/O	User defined
J3.D30	DGND	DGND	-	-	G	-	Digital ground
J3.D31	IO_L11P_T1U_N8_GC_64	FPGA.IO_L11P_T1U_N8_GC_64	AH7	Bank 64	I/O	User defined
J3.D32	IO_L11N_T1U_N9_GC_64	FPGA.IO_L11N_T1U_N9_GC_64	AJ7	Bank 64	I/O	User defined
J3.D33	DGND	DGND	-	-	G	-	Digital ground
J3.D34	IO_L9P_T1L_N4_AD12P_64	FPGA.IO_L9P_T1L_N4_AD12P_64	AH9	Bank 64	I/O	User defined
J3.D35	IO_L9N_T1L_N5_AD12N_64	FPGA.IO_L9N_T1L_N5_AD12N_64	AJ9	Bank 64	I/O	User defined
J3.D36	DGND	DGND	-	-	G	-	Digital ground
J3.D37	IO_L10P_T1U_N6_QBC_AD4P_64	FPGA.IO_L10P_T1U_N6_QBC_AD4P_64	AK9	Bank 64	I/O	User defined
J3.D38	IO_L10N_T1U_N7_QBC_AD4N_64	FPGA.IO_L10N_T1U_N7_QBC_AD4N_64	AK8	Bank 64	I/O	User defined
J3.D39	DGND	DGND	-	-	G	-	Digital ground
J3.D40	IO_T1U_N12_64	FPGA.IO_T1U_N12_64	AG9	Bank 64	I/O	User defined
J3.D41	DGND	DGND	-	-	G	-	Digital ground
J3.D42	IO_L24P_T3U_N10_64	FPGA.IO_L24P_T3U_N10_64	AF2	Bank 64	I/O	User defined
J3.D43	IO_L24N_T3U_N11_64	FPGA.IO_L24N_T3U_N11_64	AF1	Bank 64	I/O	User defined
J3.D44	DGND	DGND	-	-	G	-	Digital ground
J3.D45	IO_L22P_T3U_N6_DBC_AD0P_64	FPGA.IO_L22P_T3U_N6_DBC_AD0P_64	AG1	Bank 64	I/O	User defined
J3.D46	IO_L22N_T3U_N7_DBC_AD0N_64	FPGA.IO_L22N_T3U_N7_DBC_AD0N_64	AH1	Bank 64	I/O	User defined
J3.D47	DGND	DGND	-	-	G	-	Digital ground
J3.D48	IO_L21P_T3L_N4_AD8P_64	FPGA.IO_L21P_T3L_N4_AD8P_64	AJ2	Bank 64	I/O	User defined
J3.D49	IO_L21N_T3L_N5_AD8N_64	FPGA.IO_L21N_T3L_N5_AD8N_64	AK2	Bank 64	I/O	User defined
J3.D50	DGND	DGND	-	-	G	-	Digital ground
J3.D51	IO_L19P_T3L_N0_DBC_AD9P_64	FPGA.IO_L19P_T3L_N0_DBC_AD9P_64	AK4	Bank 64	I/O	User defined
J3.D52	IO_L19N_T3L_N1_DBC_AD9N_64	FPGA.IO_L19N_T3L_N1_DBC_AD9N_64	AK3	Bank 64	I/O	User defined
J3.D53	DGND	DGND	-	-	G	-	Digital ground
J3.D54	IO_L23P_T3U_N8_64	FPGA.IO_L23P_T3U_N8_64	AF3	Bank 64	I/O	User defined
J3.D55	IO_L23N_T3U_N9_64	FPGA.IO_L23N_T3U_N9_64	AG3	Bank 64	I/O	User defined
J3.D56	DGND	DGND	-	-	G	-	Digital ground
J3.D57	IO_L20P_T3L_N2_AD1P_64	FPGA.IO_L20P_T3L_N2_AD1P_64	AH3	Bank 64	I/O	User defined
J3.D58	IO_L20N_T3L_N3_AD1N_64	FPGA.IO_L20N_T3L_N3_AD1N_64	AH2	Bank 64	I/O	User defined
J3.D59	DGND	DGND	-	-	G	-	Digital ground
J3.D60	IO_T3U_N12_64	FPGA.IO_T3U_N12_64	AJ1	Bank 64	I/O	User defined

Power and reset

ONDA Plus SOM/ONDA Plus Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence ONDA Plus SOM/ONDA Plus Hardware/Power and Reset/Reset scheme and control signals

PL initialization signals

This page provides information about the Programmable Logic (PL) initialization signals: PS_PROGRAM_B, PS_INIT_B, and PS_DONE.

Please refer to UltraScale Architecture PCB Design User Guide for more information about the usage and configuration of the initialization circuit and signals. As described in the link, the user can initialize the PL using these PS signals.

ONDA Plus SOM signals are configured in the following way:

Pin#	Pin name	Function	Notes
J1.A33	PS_PROG_B	Signal to reset configuration block	Internal 10K Ω pull-up
J1.A34	PS_INIT_B	Initialization completion indicator after POR	Internal 10K Ω pull-up
J1.A32	PS_DONE	PL programmed DONE signal	Internal 10K Ω pull-up. It does not require any external pull-up or pull-down but can be used for connecting a user-led for a configuration completed indication (see for example ONDA EVK schematics). These signals are referenced to the Bank 503 power rail, which operates at 1.8 V (see Processing System (PS) Bank Voltage).

System boot

In order to fully understand how boot works on the ONDA Plus SOM, please refer to Chapter 11 ("Boot and configuration") of the Zynq UltraScale+ Device Technical Reference Manual (UG1085).

The BootROM can boot the system from Quad-SPI, SD, eMMC, USB 2.0 controller 0, or NAND external boot devices. All modes can be non-secure or be secure and signed except for PS JTAG and PJTAG.

The system boot-up process is managed and carried out by the platform management unit (PMU) and configuration security unit (CSU). The boot-up process consists of three functional stages.

• Pre-configuration stage
• Configuration stage
• Post-configuration stage

The PMU performs several mandatory and optional security operations; the CSU is the central configuration processor that manages secure and non-secure system-level configuration.

After a system reset, the system automatically sequences to initialize the system and process the first-stage boot loader from the selected external boot device.

Boot options

The boot ROM supports configuration from different slave interfaces, but not all of them are available in the ONDA Plus SOM. Here below the list of available boot interfaces:

• PS JTAG
• onboard QSPI 32-bit NOR flash(es)
• SD1
• onboard eMMC
• USB

Boot mode is selectable via mode pins (PS_MODE[3:0]); here below the allowed boot modes

Boot interface	BOOT_MODE[3..0]	Pin location
PS JTAG	0000	JTAG
QSPI NORE 32 bit	0010	MIO[12:00]
SD1	0101	MIO[51:43]
eMMC	0110	MIO[22:13]
USB	0111	MIO[63:52]

Default boot configuration for ONDA Plus SOM is PS_MODE[3:0] = 0110 (eMMC)

Boot sequence customization

PS_MODE[3:0] are routed to the J1 connector, enabling the customization of the boot sequence through a simple resistor network that can be implemented on the carrier board hosting the ONDA Plus SOM.

Mode signal	J1 pin	Notes
PS_MODE[3]	J1.A24	PS_MODE pins, from Bank503, are powered @ 1V8
PS_MODE[2]	J1.A23
PS_MODE[1]	J1.A22
PS_MODE[0]	J1.A21

JTAG

The Zynq UltraScale+ MPSoC JTAG interface provides 4-wire IEEE 1149.1 standard access (TCK, TMS, TDI, TDO) for debugging, programming, and boundary-scan, usually operating at 3.3V. It allows direct control over the Processing System (PS) and Programmable Logic (PL), supporting boot mode configuration (e.g., QSPI boot) and flash programming via tools like Vivado or Vitis.

JTAG signals are connected to the pinout connector (J1) on ONDA Plus.

Pin#	Pin name	Function	Notes
J1.A38	JTAG_TMS	-	-
J1.A39	JTAG_TDO	-	-
J1.A40	JTAG_TDI	-	-
J1.A41	JTAG_TCK	-	-

Peripherals

Processing System

PS_MIO pins are multiplexed I/O that can be configured to support multiple I/O interfaces. These interfaces include QSPI, USB, Ethernet, SDIO, UART, QSPI, and GPIO interfaces.

The MIO pins, on ONDA Plus SOM, are assigned as reported in the following table:

MIO Pins	Bank	VCC	Function/Peripheral	Notes
[0:5]	B500	1V8	QSPI0	Internal connection to QSPI NOR flash
6	B500		unused MIO	Available on J1.D27
[7:12]	B500		QSPI1	Internal connection to QSPI NOR flash
[13:22]	B500		SD0 interface (eMMC)	Internal connection to eMMC
23	B500		unused MIO	Available on J1.C21
[24:25]	B500		UART1	UART console
[26:37]	B501	3V3 (or externally provided with a BOM variant)	unused MIO	Available on J1.[C23..C36]
[38:39]	B501		I²C0	Internal connection to RTC, EEPROM, Temperature Monitor
[40:44]	B501		unused MIO	Available on J1.[C38..C43]
[45:51]	B501		SD1 (MMC)	External SD interface (boot)
[52:63]	B502	1V8	USB0	Internal connection to USB PHY
[64:75]	B502		Gigabit Ethernet 3 (GEM3)	Internal connection to ethernet PHY
[76]	B502		MDC (ethernet Management Data Clock input)
[77]	B502		MDIO (ethernet Management Data Input/Output)

GT transceiver

The following table reports the GT transceiver characteristics:

FPGA Bank	Type	Differentials Pairs			Ref. clock pairs
		XCZU6	XCZU9	XCZU15
Bank 505	GTR	4 TX + 4 RX			4

• GTR = PS-GTR receivers and transmitters supports up to xxx.0Gb/s data rates (supports SGMII tri-speed Ethernet, PCI Express® Gen2, Serial-ATA (SATA), USB3.0, and DisplayPort™)

DDR

The B504 bank is interfaced with DDR4 memories configured at 64-bit with 8-bit ECC.

For implementation details, see UG1085-TRM ch.17.3.4 "Error Correcting Code".

Programmable logic

The following paragraphs describe in detail the available PL I/O signals and how they are routed to the ONDA Plus connectors. The Zynq Ultrascale+ AP SoC is split into I/O banks to allow flexibility in the choice of I/O standards, each table reports one bank configuration.

Moreover, ONDA Plus design allows the carrier board to power all three PL banks for achieving complete flexibility in terms of I/O voltage levels too.

For more details about PCB design considerations, please refer to the Advanced routing and carrier board design guidelines article.

The following table reports the I/O banks characteristics:

ONDA Plus bank			FPGA Bank	Bank power supply pins	I/O	Differentials Pairs
Name	Type	External power rail	XCZU6 / 9 / 15		XCZU6 / 9 / 15	XCZU6 / 9 / 15
Bank 47	HD	VCC_B47	Bank 47	J2.[A1..A4]	24	12
Bank 48		VCC_B48	Bank 48	J2.[B1..B4]	24	12
Bank 64	HP	VCC_B64	Bank 64	J3.[C1..C3, D1..D3]	48 + 4 (*)	24
Bank 65		VCC_B65	Bank 65	J3.[A1..A3, B1..B3]	48 + 4 (*)	24
Bank 66		VCC_B66	Bank 66	J2.[C1..C3, D1..D3]	48 + 4 (*)	24

FPGA I/O Bank definitions:

• HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V
• HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V
  • (*) HP banks have 24 differential pairs I/O and 4 single ended signals (each)

Max I/O

• Max HD I/O available on ONDA Plus SOM is 48 (Bank 47 and Bank 48)
• Max HP I/O available on ONDA Plus SOM is 96 (Bank 64, Bank 65 and Bank 66)

I/O naming

Each user I/O is labeled IO_Lxxy_Tmp_Nb_[opt]_##, where:

• IO indicates a user I/O pin.
• L indicates a differential pair, with xx a unique pair in the bank and y = [P|N] for the positive/negative sides of the differential pair
• T indicates the memory, with m the byte group [0-3] and p = [U|L] Upper/Low portion
• N the number within its b byte group [0 to 12]
• ## indicates the bank number
• [opt] field can be:
  • ADnny indicates a with nn a unique pair in the bank and y = [P|N] for the positive/negative sides of the differential pair
  • GC / HDGC indicates a Global Clock (GC) having access to global clock buffers adjacent to the same I/O bank, and HDGC pins have direct access to the global clock buffers
  • DBC / QBC indicates byte lane clock (DBC and QBC) input pin pairs (clock inputs directly driving source synchronous clocks)
  • VRP indicates a DCI voltage reference resistor of P transistor

GT transceiver

The following table reports the GT transceiver characteristics:

FPGA Bank	Type	Differentials Pairs			Ref. clock pairs
		XCZU6	XCZU9	XCZU15
Bank 128	GTH-L	4 TX + 4 RX			2
Bank 228	GTH-R	4 TX + 4 RX			2
Bank 229		4 TX + 4 RX			2
Bank 230		4 TX + 4 RX			2

• GTH-L = PL-GTH transceiver, on ONDA Plus the minimum data rate is 0.5Gb/s and the maximum data rates is up to 16.375Gb/s
• GTH-R = PL-GTH transceiver, on ONDA Plus the minimum data rate is 0.5Gb/s and the maximum data rates is up to 16.375Gb/s
• GTH-R and GTH-L have some physical constraints: see the related Ultrascale Architecture GTH Transceivers User Guide for more details.

Peripheral Ethernet

On-board gigabit Ethernet PHY (Microchip LAN8830) provides interface signals required to implement the 10/100/1000 Mbps Ethernet port. The transceiver is connected to the GEM3 Gigabit Ethernet Controller through the RGMII interface on MIO bank 502, pins PS_MIO[64:77]. For further details (eg: connection and selection of the magnetics), please refer to the Microchip LAN8830 datasheet.

The following table describes the interface signals:

Pin name	Conn. pin	Function	Notes
ETH_TXRX0_N	J1.B49	Media Dependent Interface[0], negative pin	-
ETH_TXRX0_P	J1.B50	Media Dependent Interface[0], positive pin	-
ETH_TXRX1_N	J1.B52	Media Dependent Interface[1], negative pin	-
ETH_TXRX1_P	J1.B53	Media Dependent Interface[1], positive pin	-
ETH_TXRX2_N	J1.B55	Media Dependent Interface[2], negative pin	-
ETH_TXRX2_P	J1.B56	Media Dependent Interface[2], positive pin	-
ETH_TXRX3_N	J1.B58	Media Dependent Interface[3], negative pin	-
ETH_TXRX3_P	J1.B59	Media Dependent Interface[3], positive pin	-
PS_MIO76_502	-	ETH_MDC Management Data Clock input	-
PS_MIO77_502	-	ETH_MDIO Management Data Input/Output	-
ETH_INTn	J1.B41	Ethernet PHY interrupt	-
ETH_RSTn	J2.B42	Ethernet reset interrupt	PHY reset is also driven by RSTn SOM_PER_RSTn signal. See Reset scheme and control signals page for more information
ETH_LED1	J1.B47	Activity LED	-
ETH_LED2	J1.B46	Link LED	-
ETH_LED3	J1.B45	LED3	-
ETH_LED4	J1.B44	LED4	-

Peripheral SDIO

The two SD/SDIO controller controllers are compatible with the standard SD Host Controller Specification Version 3.0. The controllers communicate with SDIO devices and SD memory cards with data transfers in 1-bit and 4-bit modes.

The SDIO Card Interface supports the maximum data rate in Standard mode (19 MHz), High-speed mode (50 MHz), SDR12 (25 MHz), SDR25 (50 MHz), SDR50 (100 MHz), SDR104 (200 MHz), DDR50 mode (50 MHz).

The following table describes the external ONDA Plus interface signals for the SD card interface (MIO bank 501, pins PS_MIO[46:51] and optional PS_MIO[43], PS_MIO[45]):

Pin name	Conn. pin	Function	Notes
PS_MIO45_501	J1.C44	SD/SDIO/MMC CD	Card detect (optional) pin
PS_MIO46_501	J1.C46	SD/SDIO/MMC data 0	-
PS_MIO47_501	J1.C47	SD/SDIO/MMC data 1	-
PS_MIO48_501	J1.C48	SD/SDIO/MMC data 2	-
PS_MIO49_501	J1.C49	SD/SDIO/MMC data 3	-
PS_MIO50_501	J1.C51	SD/SDIO/MMC command	-
PS_MIO51_501	J1.C52	SD/SDIO/MMC clock	-

These signals are referenced to VCC_B501 (see dedicated section in the hardware manual).

Peripheral eMMC

The second SD/SDIO controller is used for interfacing the on-board eMMC and can operate at the maximum clock rate in Standard mode (25 MHz), High-speed SDR mode (50 MHz), High-Speed DDR mode (50 MHz), HS200 mode (200 MHz). The SD/SDIO controller supports MMC4.51.

The following table describes the external ONDA Plus interface signals for the eMMC interface (MIO bank 500, pins PS_MIO[13:21]):

Pin name	Conn. pin	Function	Notes
PS_MIO13_500	-	eMMC D0	-
PS_MIO14_500	-	eMMC D1	-
PS_MIO15_500	-	eMMC D2	-
PS_MIO16_500	-	eMMC D3	-
PS_MIO17_500	-	eMMC D4	-
PS_MIO18_500	-	eMMC D5	-
PS_MIO19_500	-	eMMC D6	-
PS_MIO20_500	-	eMMC D7	-
PS_MIO21_500	-	eMMC CMD	-
PS_MIO22_500	-	eMMC CLK	-

Peripheral QSPI

The two Quad-SPI controllers are configured to operate in a dual SS parallel configuration with two NOR SPI memory devices (bootable storage).

The controller supports up to two SPI flash memories operating in parallel: in this configuration, the maximum addressable SPI flash memory is 32 MB (25-bit address).

The following table describes the interface signals (MIO bank 500, pins PS_MIO[00:12]):

Pin name	Conn. pin	Function	Notes
PS_MIO00_500	-	QSPI0 serial clock	NOR0 SCK
PS_MIO01_500	-	QSPI0 IO1	NOR0 IO pin 1
PS_MIO02_500	-	QSPI0 IO2	NOR0 IO pin 2
PS_MIO03_500	-	QSPI0 IO3	NOR0 IO pin 3
PS_MIO04_500	-	QSPI0 IO0	NOR0 IO pin 0
PS_MIO05_500	-	QSPI0 chip select	NOR0 CS#
PS_MIO07_500	-	QSPI1 chip select	NOR1 CS#
PS_MIO08_500	-	QSPI1 IO0	NOR1 IO pin 0
PS_MIO09_500	-	QSPI1 IO1	NOR1 IO pin 1
PS_MIO010_500	-	QSPI1 IO2	NOR1 IO pin 2
PS_MIO011_500	-	QSPI1 IO3	NOR1 IO pin 3
PS_MIO012_500	-	QSPI1 serial clock	NOR1 SCK

Peripheral I2C

This I²C module is a bus controller that can function as a master or a slave in a multi-master design. It supports an extremely wide clock frequency range up to 400 Kb/s.

An internal voltage level translator allows the use of MIO Bank 501 signals with a different voltage level than the internal 3V3-powered devices: the I²C0 is internally connected to the following devices:

• Temperature_Monitor: Texas Instruments TMP421 (Address: 0x4F)
• Real Time Clock: Maxim Integrated DS3232M (Address: 0x68)

The following table describes the interface signals:

Pin name	Conn. pin	Function	Notes
PS_MIO38_501	J1.A53	I2C SCL	-
PS_MIO39_501	J1.A54	I2C SDA	-

These signals are referenced to VCC_B501 (see dedicated section in the hardware manual).

Peripheral UART

The UART controller is a full-duplex asynchronous receiver and transmitter that supports a wide range of programmable baud rates and I/O signal formats. UART1 port is routed to the SOM connectors as a 2-wire interface. The following table describes the interface signals:

Pin name	Conn. pin	Function	Notes
PS_MIO24_500	J1.A58	UART TX	-
PS_MIO25_500	J1.A59	UART RX	-

These signals are referenced to VCC_B500 (see dedicated section in the hardware manual).

Peripheral USB

ONDA Plus provides one USB 2.0 (Full Speed, up to 480 Mbps) port with on-board USB3317 PHY Hi-Speed and support to the On-The-Go (OTG) specifications. The transceiver is connected to the USB1 controller (MIO bank 502, pins PS_MIO[52:63]). The following table describes the interface signals:

Pin name	Conn. pin	Function	Notes
USB_D_P	J1.B38	D+ pin of the USB cable	-
USB_D_N	J1.B39	D- pin of the USB cable	-
USB_RST	J1.B33	USB PHY reset signal	-
USB_VBUS	J1.B34	VBUS pin of the USB cable	-
USB_CPEN	J1.B35	External 5 volt supply enable	This pin is used to enable the external VBUS power supply
USB_ID	J1.B36	ID pin of the USB cable	For non-OTG applications this pin can be floated. For an A-device ID is grounded. For a B-device ID is floated.

These signals are referenced to 1V8 (see dedicated section in the hardware manual).

Peripheral RTC

An on-board Maxim Integrated DS3232M device provides a very accurate, temperature-compensated real-time clock (RTC) resource with:

• Temperature-compensated crystal oscillator
• Date, time and calendar
• Alarm capability
• Backup power from external battery
• ±3.5ppm accuracy from -40°C to +85°C
• 236 Bytes of Battery-Backed SRAM
• I²C Interface

For a detailed description of RTC characteristics, please refer to the DS3232M datasheet.

Signals

Pin#	Pin name	Function	Notes
J1.A49	RTC_32KHZ	32.768kHz output	-
J1.A51	RTC_RSTn	active-low reset	open-drain input/output
J1.A50	RTC_INTn/SQW	active-Low Interrupt or 1Hz Square-Wave Output	It can be left open if not used.
J1.A48	RTC_VBAT	Backup power	If not used, RTC_VBAT must be externally connected to GND

These signals are referenced to 3.3VIN auxiliary input PS.

Default configuration

MAX6373 timeout is pin-selectable. It can be configured through the WDT_SET0, WDT_SET1 and WDT_SET2 signals. By default, they are configured as follows:

• WD_SET2 = 0
• WD_SET1 = 1
• WD_SET0 = 1

This set selects the option disabled(the exhaustive list of configurations options is descripted on MAX6373 page 4 datasheet):

Watchdog signals

Watchdog signals are connected to the pinout connector J1 on ONDA Plus.

Pin#	Pin name	Function	Notes
J1.A45	WDT_SET2	SET2	Internal 10K Ω pull-down
J1.A44	WDT_SET1	SET1	Internal 10K Ω pull-up
J1.A43	WDT_SET0	SET0	Internal 10K Ω pull-up
J1.A46	WDT_REARM	WDI	Internal 10K Ω pull-down
J1.A28	WDT_RST	WDO	For further details, please refer to Reset_scheme_and_control_signals WDO can be optionally connected to the PS_POR_B signal (J1.26 pin): contact sales dept. for more information.

When the watchdog is started, the software (bootloader/operating system) must take care of toggling the watchdog trigger pin (WDI) before the timeout expiration.

Selecting different configurations

Since WD_SETx signals are routed externally, WDT configuration can be changed by optional circuitry implemented on the carrier board. Different solutions can be implemented on the carrier board, depending on system requirements. The easiest circuit consists of additional stronger pull-up/down resistors connected to WDT_SETx pins in order to overrule default configuration. As MAX6373 allows to change the configuration during operation, more complex solutions can be implemented as well.

Peripheral Temperature Monitor

An on-board thermal IC (Texas Instruments TMP421) connected to the I²C interface can work as a local temperature sensor, providing the measurement of its internal temperature, but also as a remote temperature sensor, since it is connected to the XADC_DXP/XADC_DXN of the Zynq processor, providing the measurement of the Zynq internal temperature.

For a detailed description of the thermal IC characteristics, please refer to the TMP421 datasheet.

Electrical, Thermal and Mechanical Features

Operational characteristics

Absolute Maximum ratings

Parameter	Min	Typ	Max	Unit
Main power supply voltage	-0.3	3.3	3.4	V

Recommended ratings

Parameter	Min	Typ	Max	Unit
Main power supply voltage	3.135	3.3	3.4	V

Programmable Logic (PL) Bank Voltage support

The power supplies of PL banks are provided by the carrier board.

Please refer to the dedicated section in the hardware manual for PL Voltage levels.

Processing System (PS) Bank Voltage support

The PS bank are powered by the SOM.

Please refer to the dedicated section in the hardware manual for PS Voltage levels.

Power consumption

Providing a theoretical maximum power consumption value would be useless for the majority of system designers building their application upon ONDA Plus SOM because, in most cases, this would lead to an oversized power supply unit.

Please note that ONDA Plus platform is so flexible that it is virtually impossible to test for all possible configurations and applications on the market.

Generally speaking, application-specific requirements must be taken into account to properly design the power supply unit and to implement the thermal management.

ONDA Plus SOM/ONDA Plus Hardware/Electrical Thermal and Mechanical Features/Thermal management and heat dissipation

Mechanical specifications

This chapter describes the mechanical characteristics of the ONDA Plus module.

Board Layout

The following figure shows the physical dimensions of the ONDA Plus module:

The following figure highlights the maximum components' heights (expressed in mm) in the ONDA Plus SOM:

CAD drawings

• STEP (3D)