ONDA Plus SOM/ONDA Plus Hardware/pdf

General Information

BORA Block Diagram

ONDA Plus Block diagram

BORA TOP View

ONDA Plus TOP View

BORA BOTTOM View

ONDA Plus BOTTOM View

Processor and memory subsystem

The heart of ONDA Plus module is composed by the following components:

• Xilinx Zynq Ultrascale+ XCZU6EG / XCZU9EG or XCZU15EG SoC
• Power supply unit
• DDR memory banks
• NOR and eMMC flash storage
• 3x 240 pin connectors with interfaces signals

This chapter shortly describes the main ONDA Plus components.

Processor Info

Table: XCZUxxEG models comparison

Processor	XCZUxxEG
# Cores	4x Arm® Cortex®-A53 2x Arm® Cortex®-MRF
Clocks	Cortex®-A53 up to 1.5 GHz Cortex®-MRF up to 600 MHz
L2 Cache	1 MB
OchChip RAM	256 KB
DDR4	64 bit @ 2400 MHz
GPU	ARM Mali-400 up to 667 MHz OpenGL ES 1.1 and Open VG 1.1
Ethernet	1 Gbit/s MAC (with 3 additional RGMII)
PCIe	x1, x2 and x4 Gen2 (2.1 base specification)
USB	USB 2.0
Serial Interfaces	UART, CAN, I2C, SPI

PL info

The Zynq™Ultrascale+ MPSoCs have software, hardware, interconnect, power, security, and I/O programmability. The range of devices in the Zynq UltraScale+ MPSoC family allows designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools.

The Zynq UltraScale+ MPSoCs are able to serve a wide range of applications including:

• Automotive: Driver assistance, driver information, and infotainment
• Wireless Communications: Support for multiple spectral bands and smart antennas
• Wired Communications: Multiple wired communications standards and context-aware network services
• Data Centers: Software Defined Networks (SDN), data pre-processing, and analytics
• Smarter Vision: Evolving video-processing algorithms, object detection, and analytics
• Connected Control/M2M: Flexible/adaptable manufacturing, factory throughput, quality, and safet

ONDA Plus can mount three versions of the Zynq US+ processor. The following table shows the main PL features:

Table: XCZUxxEG features

Processor	Programmable logic cells	LUTs	Flip flops	Distributed RAM	Total Block RAM	DSP slices	Serial Tranceivers	Peak Serial Transceiver performance
XCZU6EG	469K Logic Cells	214604	429208	6.9 Mb	25.1 Mb	1973	4	10 Gb/s (*)
XCZU9EG	600K Logic Cells	274080	548160	8.8 Mb	32.1 Mb	2520	4	10 Gb/s (*)
XCZU15EG	746K Logic Cells	341280	682560	11.3 Mb	26.2 Mb	3528	4	10 Gb/s (*)

(*) tested connectors bandwidth

RAM memory bank

DDR4 RAM memory bank is composed by 64-bit width chips. The following table reports the RAM specifications:

CPU connection	Dynamic Memory Controller (DDRC)
Size max	16 GB
Width	64 bit with hardware ECC
Speed	3200 MHz

NOR flash bank

NOR flash is a Serial Peripheral Interface (SPI) device. By default two devices are connected to both QSPI channel 0 and channel 1 for a dual parallel interface. They acts as boot memory. The following table reports the NOR flash specifications:

CPU connection	PS MIO QSPI Channel 0 / 1
Size min	16 MB
Size max	32 MB
Chip select	SS5 and SS7
Bootable	Yes

eMMC flash bank

On board main storage memory eMMC is connected to the PS MIO interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:

CPU connection	PS MIO SDIO0
Size min	8 GB
Size max	128 GB
Bootable	Yes

Power supply unit

ONDA Plus embeds all the elements required for powering the unit, so the power sequencing is self-contained and simplified. Nevertheless, power must be provided from the carrier board, and therefore users should be aware of the power supply ranges that can be assumed as well as all other parameters.

Hardware versioning and tracking

ONDA Plus SOM implements well established versioning and tracking mechanisms:

• PCB version is copper printed on PCB itself, as shown in Fig. 1
• serial number: it is printed on a white label, as shown in Fig. 2: see also Product serial number page for more details
• ConfigID: it is used by software running on the board for the identification of the product model/hardware configuration. For more details, please refer to this link
  • on ONDA Plus SOM ConfigID is stored in an internal I2C EEPROM

Fig.1 PCB version

Fig.2 Serial number

Part number composition

ONDA Plus SOM module part number is identified by the following digit-code table:

Part number structure	Options	Description
Family	NDP	Family prefix code
SOC	0: XCZU6EG Quad-core Cortex-A53 @1.5 GHz, Dual-core Cortex-R5F @600 MHz 1: XCZU9EG Quad-core Cortex-A53 @1.5 GHz, Dual-core Cortex-R5F @600 MHz 2: XCZU15EG Quad-core Cortex-A53 @1.5 GHz, Dual-core Cortex-R5F @600 MHz 3: XQZU9EG Quad-core Cortex-A53 @1.5 GHz, Dual-core Cortex-R5F @600 MHz 4: XQZU15EG Quad-core Cortex-A53 @1.5 GHz, Dual-core Cortex-R5F @600 MHz	Other versions can be available, please contact technical support
RAM	4: 4GB DDR4 with ECC
Storage	0: 128GB eMMC pSLC and 32MB NOR
RFU	0: Default
Mounting options	0: PL banks 47, 48, 64, 65, 66 1V8 fixed 1: PL banks 47, 48 @1V8, 64, 65, 66 1V8 external power supply
Temperature range	C - Commercial grade: suitable for 0-70°C environment I - Industrial grade: suitable for 40 - 85°C environment
PCB revision	0: first version 1: PCB rev. A	PCB release may change for manufacturing purposes (i.e. text fixture adaptation)
Manufacturing option	N: No-RoHS R: RoHS compliant S: Leaded (SnPb) No-RoHS	typically connected to production process and quality
Software Configuration	-00: standard factory u-boot pre-programmed	If customers require custom SW deployed this section should be defined and agreed. Please contact technical support

Example

ONDA PLUS SOM code NDP44001I1R-00

• 4: XQZU15EG Quad core A53 1.5GHz / Dual core R5F
• 4: 4GB DDR4
• 0: 128GB eMMC and 32MB NOR
• 0: -
• 1: PL banks 47, 48 @1V8, 64, 65, 66 1V8 external power supply
• I: Industrial grade: -40 to +85°C
• 1: PCB version rev. A
• R: RoHS compliant
• -00: standard factory u-boot pre-programmed

Pinout Table

ONDA Plus SOM/ONDA Plus Hardware/Pinout Table

Power and reset

ONDA Plus SOM/ONDA Plus Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence ONDA Plus SOM/ONDA Plus Hardware/Power and Reset/Reset scheme and control signals

PL initialization signals

This page provides information about the Programmable Logic (PL) initialization signals: PS_PROGRAM_B, PS_INIT_B, and PS_DONE.

Please refer to UltraScale Architecture PCB Design User Guide for more information about the usage and configuration of the initialization circuit and signals. As described in the link, the user can initialize the PL using these PS signals.

ONDA Plus SOM signals are configured in the following way:

Pin#	Pin name	Function	Notes
J1.A33	PS_PROG_B	Signal to reset configuration block	Internal 10K Ω pull-up
J1.A34	PS_INIT_B	Initialization completion indicator after POR	Internal 10K Ω pull-up
J1.A32	PS_DONE	PL programmed DONE signal	Internal 10K Ω pull-up. It does not require any external pull-up or pull-down but can be used for connecting a user-led for a configuration completed indication (see for example ONDA EVK schematics). These signals are referenced to the Bank 503 power rail, which operates at 1.8 V (see Processing System (PS) Bank Voltage).

System boot

In order to fully understand how boot works on the ONDA Plus SOM, please refer to Chapter 11 ("Boot and configuration") of the Zynq UltraScale+ Device Technical Reference Manual (UG1085).

The BootROM can boot the system from Quad-SPI, SD, eMMC, USB 2.0 controller 0, or NAND external boot devices. All modes can be non-secure or be secure and signed except for PS JTAG and PJTAG.

The system boot-up process is managed and carried out by the platform management unit (PMU) and configuration security unit (CSU). The boot-up process consists of three functional stages.

• Pre-configuration stage
• Configuration stage
• Post-configuration stage

The PMU performs several mandatory and optional security operations; the CSU is the central configuration processor that manages secure and non-secure system-level configuration.

After a system reset, the system automatically sequences to initialize the system and process the first-stage boot loader from the selected external boot device.

Boot options

The boot ROM supports configuration from different slave interfaces, but not all of them are available in the ONDA Plus SOM. Here below the list of available boot interfaces:

• PS JTAG
• onboard QSPI 32-bit NOR flash(es)
• SD1
• onboard eMMC
• USB

Boot mode is selectable via mode pins (PS_MODE[3:0]); here below the allowed boot modes

Boot interface	BOOT_MODE[3..0]	Pin location
PS JTAG	0000	JTAG
QSPI NORE 32 bit	0010	MIO[12:00]
SD1	0101	MIO[51:43]
eMMC	0110	MIO[22:13]
USB	0111	MIO[63:52]

Default boot configuration for ONDA Plus SOM is PS_MODE[3:0] = 0110 (eMMC)

Boot sequence customization

PS_MODE[3:0] are routed to the J1 connector, enabling the customization of the boot sequence through a simple resistor network that can be implemented on the carrier board hosting the ONDA Plus SOM.

Mode signal	J1 pin	Notes
PS_MODE[3]	J1.A24	PS_MODE pins, from Bank503, are powered @ 1V8
PS_MODE[2]	J1.A23
PS_MODE[1]	J1.A22
PS_MODE[0]	J1.A21

JTAG

The Zynq UltraScale+ MPSoC JTAG interface provides 4-wire IEEE 1149.1 standard access (TCK, TMS, TDI, TDO) for debugging, programming, and boundary-scan, usually operating at 3.3V. It allows direct control over the Processing System (PS) and Programmable Logic (PL), supporting boot mode configuration (e.g., QSPI boot) and flash programming via tools like Vivado or Vitis.

JTAG signals are connected to the pinout connector (J1) on ONDA Plus.

Pin#	Pin name	Function	Notes
J1.A38	JTAG_TMS	-	-
J1.A39	JTAG_TDO	-	-
J1.A40	JTAG_TDI	-	-
J1.A41	JTAG_TCK	-	-

Peripherals

Processing System

PS_MIO pins are multiplexed I/O that can be configured to support multiple I/O interfaces. These interfaces include QSPI, USB, Ethernet, SDIO, UART, QSPI, and GPIO interfaces.

The MIO pins, on ONDA Plus SOM, are assigned as reported in the following table:

MIO Pins	Bank	VCC	Function/Peripheral	Notes
[0:5]	B500	1V8	QSPI0	Internal connection to QSPI NOR flash
6	B500		unused MIO	Available on J1.D27
[7:12]	B500		QSPI1	Internal connection to QSPI NOR flash
[13:22]	B500		SD0 interface (eMMC)	Internal connection to eMMC
23	B500		unused MIO	Available on J1.C21
[24:25]	B500		UART1	UART console
[26:37]	B501	3V3 (or externally provided with a BOM variant)	unused MIO	Available on J1.[C23..C36]
[38:39]	B501		I²C0	Internal connection to RTC, EEPROM, Temperature Monitor
[40:44]	B501		unused MIO	Available on J1.[C38..C43]
[45:51]	B501		SD1 (MMC)	External SD interface (boot)
[52:63]	B502	1V8	USB0	Internal connection to USB PHY
[64:75]	B502		Gigabit Ethernet 3 (GEM3)	Internal connection to ethernet PHY
[76]	B502		MDC (ethernet Management Data Clock input)
[77]	B502		MDIO (ethernet Management Data Input/Output)

GT transceiver

These page reports the GT transceiver characteristics.

Programmable logic

The following paragraphs describe in detail the available PL I/O signals and how they are routed to the ONDA Plus connectors. The Zynq Ultrascale+ AP SoC is split into I/O banks to allow flexibility in the choice of I/O standards, each table reports one bank configuration.

Moreover, ONDA Plus design allows the carrier board to power all three PL banks for achieving complete flexibility in terms of I/O voltage levels too.

For more details about PCB design considerations, please refer to the Advanced routing and carrier board design guidelines article.

The following table reports the I/O banks characteristics:

ONDA Plus bank			FPGA Bank	Bank power supply pins	I/O	Differentials Pairs
Name	Type	External power rail	XCZU6 / 9 / 15		XCZU6 / 9 / 15	XCZU6 / 9 / 15
Bank 47	HD	VCC_B47	Bank 47	J2.[A1..A4]	24	12
Bank 48		VCC_B48	Bank 48	J2.[B1..B4]	24	12
Bank 64	HP	VCC_B64	Bank 64	J3.[C1..C3, D1..D3]	48 + 4 (*)	24
Bank 65		VCC_B65	Bank 65	J3.[A1..A3, B1..B3]	48 + 4 (*)	24
Bank 66		VCC_B66	Bank 66	J2.[C1..C3, D1..D3]	48 + 4 (*)	24

FPGA I/O Bank definitions:

• HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V
• HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V
  • (*) HP banks have 24 differential pairs I/O and 4 single ended signals (each)

Max I/O

• Max HD I/O available on ONDA Plus SOM is 48 (Bank 47 and Bank 48)
• Max HP I/O available on ONDA Plus SOM is 96 (Bank 64, Bank 65 and Bank 66)

I/O naming

Each user I/O is labeled IO_Lxxy_Tmp_Nb_[opt]_##, where:

• IO indicates a user I/O pin.
• L indicates a differential pair, with xx a unique pair in the bank and y = [P|N] for the positive/negative sides of the differential pair
• T indicates the memory, with m the byte group [0-3] and p = [U|L] Upper/Low portion
• N the number within its b byte group [0 to 12]
• ## indicates the bank number
• [opt] field can be:
  • ADnny indicates a with nn a unique pair in the bank and y = [P|N] for the positive/negative sides of the differential pair
  • GC / HDGC indicates a Global Clock (GC) having access to global clock buffers adjacent to the same I/O bank, and HDGC pins have direct access to the global clock buffers
  • DBC / QBC indicates byte lane clock (DBC and QBC) input pin pairs (clock inputs directly driving source synchronous clocks)
  • VRP indicates a DCI voltage reference resistor of P transistor

GT transceiver

The following table reports the GT transceiver characteristics:

FPGA Bank	Domain	Type	Differentials Pairs			Ref. clock pairs
			XCZU6	XCZU9	XCZU15
Bank 505	PS	GTR	4 TX + 4 RX			4
Bank 128	PL	GTH-L	4 TX + 4 RX			2
Bank 228		GTH-R	4 TX + 4 RX			2
Bank 229			4 TX + 4 RX			2
Bank 230			4 TX + 4 RX			2

• GTR = PS-GTR receivers and transmitters supports up to xxx.0Gb/s data rates (supports SGMII tri-speed Ethernet, PCI Express® Gen2, Serial-ATA (SATA), USB3.0, and DisplayPort™)
• GTH-L = PL-GTH transceiver, on ONDA Plus the minimum data rate is 0.5Gb/s and the maximum data rates is up to 16.375Gb/s
• GTH-R = PL-GTH transceiver, on ONDA Plus the minimum data rate is 0.5Gb/s and the maximum data rates is up to 16.375Gb/s
• GTH-R and GTH-L have some physical constraints: see the related Ultrascale Architecture GTH Transceivers User Guide for more details

Peripheral Ethernet

On-board gigabit Ethernet PHY (Microchip LAN8830) provides interface signals required to implement the 10/100/1000 Mbps Ethernet port. The transceiver is connected to the GEM3 Gigabit Ethernet Controller through the RGMII interface on MIO bank 502, pins PS_MIO[64:77]. For further details (eg: connection and selection of the magnetics), please refer to the Microchip LAN8830 datasheet.

The following table describes the interface signals:

Pin name	Conn. pin	Function	Notes
ETH_TXRX0_N	J1.B49	Media Dependent Interface[0], negative pin	-
ETH_TXRX0_P	J1.B50	Media Dependent Interface[0], positive pin	-
ETH_TXRX1_N	J1.B52	Media Dependent Interface[1], negative pin	-
ETH_TXRX1_P	J1.B53	Media Dependent Interface[1], positive pin	-
ETH_TXRX2_N	J1.B55	Media Dependent Interface[2], negative pin	-
ETH_TXRX2_P	J1.B56	Media Dependent Interface[2], positive pin	-
ETH_TXRX3_N	J1.B58	Media Dependent Interface[3], negative pin	-
ETH_TXRX3_P	J1.B59	Media Dependent Interface[3], positive pin	-
PS_MIO76_502	-	ETH_MDC Management Data Clock input	-
PS_MIO77_502	-	ETH_MDIO Management Data Input/Output	-
ETH_INTn	J1.B41	Ethernet PHY interrupt	-
ETH_RSTn	J2.B42	Ethernet reset interrupt	PHY reset is also driven by RSTn SOM_PER_RSTn signal. See Reset scheme and control signals page for more information
ETH_LED1	J1.B47	Activity LED	-
ETH_LED2	J1.B46	Link LED	-
ETH_LED3	J1.B45	LED3	-
ETH_LED4	J1.B44	LED4	-

Peripheral SDIO

The two SD/SDIO controller controllers are compatible with the standard SD Host Controller Specification Version 3.0. The controllers communicate with SDIO devices and SD memory cards with data transfers in 1-bit and 4-bit modes.

The SDIO Card Interface supports the maximum data rate in Standard mode (19 MHz), High-speed mode (50 MHz), SDR12 (25 MHz), SDR25 (50 MHz), SDR50 (100 MHz), SDR104 (200 MHz), DDR50 mode (50 MHz).

The following table describes the external ONDA Plus interface signals for the SD card interface (MIO bank 501, pins PS_MIO[46:51] and optional PS_MIO[43], PS_MIO[45]):

Pin name	Conn. pin	Function	Notes
PS_MIO45_501	J1.C44	SD/SDIO/MMC CD	Card detect (optional) pin
PS_MIO46_501	J1.C46	SD/SDIO/MMC data 0	-
PS_MIO47_501	J1.C47	SD/SDIO/MMC data 1	-
PS_MIO48_501	J1.C48	SD/SDIO/MMC data 2	-
PS_MIO49_501	J1.C49	SD/SDIO/MMC data 3	-
PS_MIO50_501	J1.C51	SD/SDIO/MMC command	-
PS_MIO51_501	J1.C52	SD/SDIO/MMC clock	-

These signals are referenced to VCC_B501 (see dedicated section in the hardware manual).

Peripheral eMMC

The second SD/SDIO controller is used for interfacing the on-board eMMC and can operate at the maximum clock rate in Standard mode (25 MHz), High-speed SDR mode (50 MHz), High-Speed DDR mode (50 MHz), HS200 mode (200 MHz). The SD/SDIO controller supports MMC4.51.

The following table describes the external ONDA Plus interface signals for the eMMC interface (MIO bank 500, pins PS_MIO[13:21]):

Pin name	Conn. pin	Function	Notes
PS_MIO13_500	-	eMMC D0	-
PS_MIO14_500	-	eMMC D1	-
PS_MIO15_500	-	eMMC D2	-
PS_MIO16_500	-	eMMC D3	-
PS_MIO17_500	-	eMMC D4	-
PS_MIO18_500	-	eMMC D5	-
PS_MIO19_500	-	eMMC D6	-
PS_MIO20_500	-	eMMC D7	-
PS_MIO21_500	-	eMMC CMD	-
PS_MIO22_500	-	eMMC CLK	-

Peripheral QSPI

The two Quad-SPI controllers are configured to operate in a dual SS parallel configuration with two NOR SPI memory devices (bootable storage).

The controller supports up to two SPI flash memories operating in parallel: in this configuration, the maximum addressable SPI flash memory is 32 MB (25-bit address).

The following table describes the interface signals (MIO bank 500, pins PS_MIO[00:12]):

Pin name	Conn. pin	Function	Notes
PS_MIO00_500	-	QSPI0 serial clock	NOR0 SCK
PS_MIO01_500	-	QSPI0 IO1	NOR0 IO pin 1
PS_MIO02_500	-	QSPI0 IO2	NOR0 IO pin 2
PS_MIO03_500	-	QSPI0 IO3	NOR0 IO pin 3
PS_MIO04_500	-	QSPI0 IO0	NOR0 IO pin 0
PS_MIO05_500	-	QSPI0 chip select	NOR0 CS#
PS_MIO07_500	-	QSPI1 chip select	NOR1 CS#
PS_MIO08_500	-	QSPI1 IO0	NOR1 IO pin 0
PS_MIO09_500	-	QSPI1 IO1	NOR1 IO pin 1
PS_MIO010_500	-	QSPI1 IO2	NOR1 IO pin 2
PS_MIO011_500	-	QSPI1 IO3	NOR1 IO pin 3
PS_MIO012_500	-	QSPI1 serial clock	NOR1 SCK

Peripheral I2C

This I²C module is a bus controller that can function as a master or a slave in a multi-master design. It supports an extremely wide clock frequency range up to 400 Kb/s.

An internal voltage level translator allows the use of MIO Bank 501 signals with a different voltage level than the internal 3V3-powered devices: the I²C0 is internally connected to the following devices:

• Temperature_Monitor: Texas Instruments TMP421 (Address: 0x4F)
• Real Time Clock: Maxim Integrated DS3232M (Address: 0x68)

The following table describes the interface signals:

Pin name	Conn. pin	Function	Notes
PS_MIO38_501	J1.A53	I2C SCL	-
PS_MIO39_501	J1.A54	I2C SDA	-

These signals are referenced to VCC_B501 (see dedicated section in the hardware manual).

Peripheral UART

The UART controller is a full-duplex asynchronous receiver and transmitter that supports a wide range of programmable baud rates and I/O signal formats. UART1 port is routed to the SOM connectors as a 2-wire interface. The following table describes the interface signals:

Pin name	Conn. pin	Function	Notes
PS_MIO24_500	J1.A58	UART TX	-
PS_MIO25_500	J1.A59	UART RX	-

These signals are referenced to VCC_B500 (see dedicated section in the hardware manual).

Peripheral USB

ONDA Plus provides one USB 2.0 (Full Speed, up to 480 Mbps) port with on-board USB3317 PHY Hi-Speed and support to the On-The-Go (OTG) specifications. The transceiver is connected to the USB1 controller (MIO bank 502, pins PS_MIO[52:63]). The following table describes the interface signals:

Pin name	Conn. pin	Function	Notes
USB_D_P	J1.B38	D+ pin of the USB cable	-
USB_D_N	J1.B39	D- pin of the USB cable	-
USB_RST	J1.B33	USB PHY reset signal	-
USB_VBUS	J1.B34	VBUS pin of the USB cable	-
USB_CPEN	J1.B35	External 5 volt supply enable	This pin is used to enable the external VBUS power supply
USB_ID	J1.B36	ID pin of the USB cable	For non-OTG applications this pin can be floated. For an A-device ID is grounded. For a B-device ID is floated.

These signals are referenced to 1V8 (see dedicated section in the hardware manual).

Peripheral RTC

An on-board Maxim Integrated DS3232M device provides a very accurate, temperature-compensated real-time clock (RTC) resource with:

• Temperature-compensated crystal oscillator
• Date, time and calendar
• Alarm capability
• Backup power from external battery
• ±3.5ppm accuracy from -40°C to +85°C
• 236 Bytes of Battery-Backed SRAM
• I²C Interface

For a detailed description of RTC characteristics, please refer to the DS3232M datasheet.

Signals

Pin#	Pin name	Function	Notes
J1.A49	RTC_32KHZ	32.768kHz output	-
J1.A51	RTC_RSTn	active-low reset	open-drain input/output
J1.A50	RTC_INTn/SQW	active-Low Interrupt or 1Hz Square-Wave Output	It can be left open if not used.
J1.A48	RTC_VBAT	Backup power	If not used, RTC_VBAT must be externally connected to GND

These signals are referenced to 3.3VIN auxiliary input PS.

Default configuration

MAX6373 timeout is pin-selectable. It can be configured through the WDT_SET0, WDT_SET1 and WDT_SET2 signals. By default, they are configured as follows:

• WD_SET2 = 0
• WD_SET1 = 1
• WD_SET0 = 1

This set selects the option disabled(the exhaustive list of configurations options is descripted on MAX6373 page 4 datasheet):

Watchdog signals

Watchdog signals are connected to the pinout connector J1 on ONDA Plus.

Pin#	Pin name	Function	Notes
J1.A45	WDT_SET2	SET2	Internal 10K Ω pull-down
J1.A44	WDT_SET1	SET1	Internal 10K Ω pull-up
J1.A43	WDT_SET0	SET0	Internal 10K Ω pull-up
J1.A46	WDT_REARM	WDI	Internal 10K Ω pull-down
J1.A28	WDT_RST	WDO	For further details, please refer to Reset_scheme_and_control_signals WDO can be optionally connected to the PS_POR_B signal (J1.26 pin): contact sales dept. for more information.

When the watchdog is started, the software (bootloader/operating system) must take care of toggling the watchdog trigger pin (WDI) before the timeout expiration.

Selecting different configurations

Since WD_SETx signals are routed externally, WDT configuration can be changed by optional circuitry implemented on the carrier board. Different solutions can be implemented on the carrier board, depending on system requirements. The easiest circuit consists of additional stronger pull-up/down resistors connected to WDT_SETx pins in order to overrule default configuration. As MAX6373 allows to change the configuration during operation, more complex solutions can be implemented as well.

Peripheral Temperature Monitor

An on-board thermal IC (Texas Instruments TMP421) connected to the I²C interface can work as a local temperature sensor, providing the measurement of its internal temperature, but also as a remote temperature sensor, since it is connected to the XADC_DXP/XADC_DXN of the Zynq processor, providing the measurement of the Zynq internal temperature.

For a detailed description of the thermal IC characteristics, please refer to the TMP421 datasheet.

Electrical, Thermal and Mechanical Features

Operational characteristics

Absolute Maximum ratings

Parameter	Min	Typ	Max	Unit
Main power supply voltage	-0.3	3.3	3.4	V

Recommended ratings

Parameter	Min	Typ	Max	Unit
Main power supply voltage	3.135	3.3	3.4	V

Programmable Logic (PL) Bank Voltage support

The power supplies of PL banks are provided by the carrier board.

Please refer to the dedicated section in the hardware manual for PL Voltage levels.

Processing System (PS) Bank Voltage support

The PS bank are powered by the SOM.

Please refer to the dedicated section in the hardware manual for PS Voltage levels.

Power consumption

Providing a theoretical maximum power consumption value would be useless for the majority of system designers building their application upon ONDA Plus SOM because, in most cases, this would lead to an oversized power supply unit.

Please note that ONDA Plus platform is so flexible that it is virtually impossible to test for all possible configurations and applications on the market.

Generally speaking, application-specific requirements must be taken into account to properly design the power supply unit and to implement the thermal management.

ONDA Plus SOM/ONDA Plus Hardware/Electrical Thermal and Mechanical Features/Thermal management and heat dissipation

Mechanical specifications

This chapter describes the mechanical characteristics of the ONDA Plus module.

Board Layout

The following figure shows the physical dimensions of the ONDA Plus module:

The following figure highlights the maximum components' heights (expressed in mm) in the ONDA Plus SOM:

CAD drawings

• STEP (3D)