ONDA Plus SOM/ONDA Plus Hardware/Peripherals/PL

History
Issue Date	Notes
2026/05/19	First documentation release

Programmable logic

The following paragraphs describe in detail the available PL I/O signals and how they are routed to the ONDA Plus connectors. The Zynq Ultrascale+ AP SoC is split into I/O banks to allow flexibility in the choice of I/O standards, each table reports one bank configuration.

Moreover, ONDA Plus design allows the carrier board to power all three PL banks for achieving complete flexibility in terms of I/O voltage levels too.

For more details about PCB design considerations, please refer to the Advanced routing and carrier board design guidelines article.

The following table reports the I/O banks characteristics:

ONDA Plus bank			FPGA Bank	Bank power supply pins	I/O	Differentials Pairs
Name	Type	External power rail	XCZU6 / 9 / 15		XCZU6 / 9 / 15	XCZU6 / 9 / 15
Bank 47	HD	VCC_B47	Bank 47	J2.[A1..A4]	24	12
Bank 48		VCC_B48	Bank 48	J2.[B1..B4]	24	12
Bank 64	HP	VCC_B64	Bank 64	J3.[C1..C3, D1..D3]	48 + 4 (*)	24
Bank 65		VCC_B65	Bank 65	J3.[A1..A3, B1..B3]	48 + 4 (*)	24
Bank 66		VCC_B66	Bank 66	J2.[C1..C3, D1..D3]	48 + 4 (*)	24

FPGA I/O Bank definitions:

• HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V
• HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V
  • (*) HP banks have 24 differential pairs I/O and 4 single ended signals (each)

Max I/O

• Max HD I/O available on ONDA Plus SOM is 48 (Bank 47 and Bank 48)
• Max HP I/O available on ONDA Plus SOM is 96 (Bank 64, Bank 65 and Bank 66)

I/O naming

Each user I/O is labeled IO_Lxxy_Tmp_Nb_[opt]_##, where:

• IO indicates a user I/O pin.
• L indicates a differential pair, with xx a unique pair in the bank and y = [P|N] for the positive/negative sides of the differential pair
• T indicates the memory, with m the byte group [0-3] and p = [U|L] Upper/Low portion
• N the number within its b byte group [0 to 12]
• ## indicates the bank number
• [opt] field can be:
  • ADnny indicates a with nn a unique pair in the bank and y = [P|N] for the positive/negative sides of the differential pair
  • GC / HDGC indicates a Global Clock (GC) having access to global clock buffers adjacent to the same I/O bank, and HDGC pins have direct access to the global clock buffers
  • DBC / QBC indicates byte lane clock (DBC and QBC) input pin pairs (clock inputs directly driving source synchronous clocks)
  • VRP indicates a DCI voltage reference resistor of P transistor

GT transceiver

The following table reports the GT transceiver characteristics:

FPGA Bank	Domain	Type	Differentials Pairs			Ref. clock pairs
			XCZU6	XCZU9	XCZU15
Bank 505	PS	GTR	4 TX + 4 RX			4
Bank 128	PL	GTH-L	4 TX + 4 RX			2
Bank 228		GTH-R	4 TX + 4 RX			2
Bank 229			4 TX + 4 RX			2
Bank 230			4 TX + 4 RX			2

• GTR = PS-GTR receivers and transmitters supports up to xxx.0Gb/s data rates (supports SGMII tri-speed Ethernet, PCI Express® Gen2, Serial-ATA (SATA), USB3.0, and DisplayPort™)
• GTH-L = PL-GTH transceiver, on ONDA Plus the minimum data rate is 0.5Gb/s and the maximum data rates is up to 16.375Gb/s
• GTH-R = PL-GTH transceiver, on ONDA Plus the minimum data rate is 0.5Gb/s and the maximum data rates is up to 16.375Gb/s
• GTH-R and GTH-L have some physical constraints: see the related Ultrascale Architecture GTH Transceivers User Guide for more details