ONDA Plus SOM/ONDA Plus Hardware/Peripherals/PS
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| Issue Date | Notes | ||
| 2026/05/18 | First documentation release | ||
Contents
Processing System[edit | edit source]
PS_MIO pins are multiplexed I/O that can be configured to support multiple I/O interfaces. These interfaces include QSPI, USB, Ethernet, SDIO, UART, QSPI, and GPIO interfaces.
The MIO pins, on ONDA Plus SOM, are assigned as reported in the following table:
| MIO Pins | Bank | VCC | Function/Peripheral | Notes |
|---|---|---|---|---|
| [0:5] | B500 | 1V8 | QSPI0 | Internal connection to QSPI NOR flash |
| 6 | B500 | unused MIO | Available on J1.D27 | |
| [7:12] | B500 | QSPI1 | Internal connection to QSPI NOR flash | |
| [13:22] | B500 | SD0 interface (eMMC) | Internal connection to eMMC | |
| 23 | B500 | unused MIO | Available on J1.C21 | |
| [24:25] | B500 | UART1 | UART console | |
| [26:37] | B501 | 3V3
(or externally provided with a BOM variant) |
unused MIO | Available on J1.[C23..C36] |
| [38:39] | B501 | I²C0 | Internal connection to RTC, EEPROM, Temperature Monitor | |
| [40:44] | B501 | unused MIO | Available on J1.[C38..C43] | |
| [45:51] | B501 | SD1 (MMC) | External SD interface (boot) | |
| [52:63] | B502 | 1V8 | USB0 | Internal connection to USB PHY |
| [64:75] | B502 | Gigabit Ethernet 3 (GEM3) | Internal connection to ethernet PHY | |
| [76] | B502 | MDC (ethernet Management Data Clock input) | ||
| [77] | B502 | MDIO (ethernet Management Data Input/Output) |
GT transceiver[edit | edit source]
These page reports the GT transceiver characteristics.
