BORA Xpress SOM/BORA Xpress Evaluation Kit/Carrier board design guidelines (SOM)

History
Issue Date	Notes
2021/11/22	New documentation layout

Carrier board design guidelines

This page provides useful information and resources to system designers to design carrier boards hosting DAVE Embedded Systems system-on-modules (SOM).

These guidelines are provided with the goal to help designers to design compliant systems with DAVE Embedded Systems modules and they cover schematics and PCB aspects. They apply to several products that are listed in the top right corner of this page (see "Applies to" boxes).

It should be noted that in a product design, it is often needed to violate some of the following guidelines as a compromise between requirements and performances. These guidelines are intended to give the carrier board designer the basic elements to make the best choices between two opposed needs and improve the overall design robustness.

Basic guidelines

In this section basic hardware guidelines valid for all DAVE Embedded Systems SOMs are detailed.

Schematics

• Check mirroring and pinout of DAVE Embedded Systems system-on-modules (SOM) connector
• Properly decouple DAVE Embedded Systems system-on-modules (SOM) power supply with a large bulk capacitor and a small bypass capacitor
• Use low-ESR X7R capacitor if possible
• Check for the correct directions of TX and RX lines
• Add termination resistors as the interface needs (see interface details)

PCB

PCB Technology

Use a PCB technology as advised in the following table

Parameter	Min	Typ	Max
Layers(number)	4	6	-
Power Plane Layers	2	4	-
Clearence(mils)	-	4	-
Trace Width(mils)	-	4	-
Vias hole (mm)	-	0,2	-
Minimum number of via for each power signal layer changes	2	3	-
Minimum number of via for each power signal SOM connector pin	1	2	-
Component package size	-	0402	-
PCB height(mm)	1,4	1,6	-

• When using vias smaller than the minimum advised size, take care to increase the number of vias to match the power signal current needs
• For vias holes agree with the manufacturer about the minimum annular ring needed for the specific PCB height
  • blind vias also need to comply to a strict aspect ratio between the hole size and depth
• PCB heights less than the minimum advised can produce PCB heating and mechanical issues

PCB Basics Guidelines

• Avoid stubs
• Isolate clock and HI-SPEED signal keeping a wider distance to the other signals (see interface specifications for further details)
• Design microstrip geometries with two reference planes layers exposed to a signal layer
• When using two signal layers between the reference layers, avoid routing parallel segments between the two layers
• Avoid HI-SPEED signals to cross power split planes that are exposed to the layer (it acts as a reference plane)
• Avoid voids on planes
• Near all HI-SPEED signal vias place a second via that connects the two reference planes (see PCB Controlled Impedance section)
• Use Solid Connection for plane vias
• Place bulk and ByPass capacitor near DAVE Embedded Systems system-on-modules (SOM) power supply pins
• Place the series terminator resistor near the related transmitter

PCB Controlled Impedance

To have reliable quality of HI-SPEED signals the correct line impedance needs to be maintained in all the signals path.

Define a valid stackup and signal geometries for each impedance profile according to the track width, distance from the reference plane(s) and the dielectric constant of the insulation material (typically FR4).

Each crest of the signal need to be considered as a wave that travel between the tracks and their reference plane(s). The higher the bandwidth, the cleaner the wavefronts must be to preserve the needed signal quality.

Any variation of the impedance along the route of a net causes a loss in the strength of the signal as a part of the signal energy is reflected backward.

Some of the possible causes are:

• change in the track width -> need to maintain the same width along all the route
• change in the distance of the reference plane -> avoid to cross split planes when they act as a reference
• vias holes -> use as little vias as possible
• large components pads -> use small SMD pads to decrease the geometry variation as well as the parassite capacitance of the pad with the reference plane

Another cause of signal decrease are the stubs.

On the bifurcation point the signal energy is split on the two path, at the dead end of the stub this energy is reflected back and then part returns to the transmitter and the other continues to the receiver but with a delay from the original wave.

The primary aspect of a stub is the length, if the stub length is much lesser than the signal wavelength the stub softens the wave crests, if the stub length is comparable to the signal wavelength it can introduce destructive interference that reduce the signal amplitude

Other than designing errors (as the net antennae), the stubs could be created (and mitigated) for the following reasons:

• routing variants
  • when a signal need to be optionally routed to more than one end. The unused end acts as a stub
  • to mitigate the issue use series components (as 0R) with one overlapped pad
• vias holes
  • when using a through vias to connect an internal layer, the section of the vias to the opposite layer is a stub
  • if a wide bandwidth is needed, the vias on critical signals can be back drilled to remove the copper on the dead end

Another aspect to be kept in mind in designing HI-SPEED signal routing is the return current of the signal that should flow in a solid, low impedance, and noise free reference plane.

There are a variety of issues caused by unmanaged return currents:

• split planes
  • causes the return currents to circumnavigate the plane and flow through the nearest bypass capacitors
  • to improve the quality of a signal that needs to cross a split plane, a local bypass capacitor, connected between the two planes, can be placed near the boundary to allow the flow of the return current
• miss of reference vias nearest the signal vias
  • when a signal travel between two layers with different reference planes, the return current should as well travel between the reference planes on the same point
  • as split planes causes a longer return path
  • if the reference planes aren't at the same potential (eg. GND and VCC), use a bypass capacitor as in the split planes case
• lack of bypass capacitors on reference planes
  • causes an increase on the plane impedance and waste of the signal energy
  • pairing a power rail plane with a GND plane creates a planar capacitor with a capacity directly proportional to the planes area and inversely proportional to the gap between the two planes
    • even if this capacity is extremely low, it can work at very high frequency as it is not affected by the parassite inductance of the vias that are needed to connect the external components to the internal planes.
• power currents
  • causes potential difference that lowers the signal quality
  • power planes are both used as reference for signal and as PDN (Power Delivery Network)
    • for critical, high bandwidth signals use a clean reference plane, different from the ones used to deliver power to the components
    • design the power planes to minimize the current density
      • check for bottlenecks in the planes from source to target
      • double the power planes to halve the current density
• parallel segments
  • causes the return currents to flow in another signal creating the crosstalk

SOM Connectors

This section provides information and suggestions regarding the SOM mating connectors.

SO-DIMM

SO-DIMM mating connectors from different vendors may have slight differences in mechanical characteristics. One critical point is the position of the end of the mating area (please see the picture below), that can be slightly shifted inwards or outwards in respect to the retention holes on the carrier board. This can lead to a misalignment with the holes on the SO-DIMM modules, making difficult or impossible to insert the retentions screws or locking supports.

If you plan to use the holes as additional retention system, we recommend to pay attention to the mechanical characteristics when evaluating the SO-DIMM mating connectors to be mounted on the carrier board.

Board to board high density

When multiple connectors are present on SoM (as well as the retention holes), the carrier board needs to place the counterparts in the exactly same relative positions. Please read the mechanical section of the hardware documentation of the SoM to check the connectors positions on the SoM

Power-up sequence

In order to prevent back powering effects, DAVE Embedded Systems' SOMs provide the signals required to handle power-up sequence properly. For instance, see the recommended sequence for the BORA SOM here.

In case the power-up sequence is not managed properly, the circuitry populating the SOM may be damaged.

Interfaces Guidelines

This section provides guidelines for the most used interfaces on DAVE Embedded Systems SOMs module.
Please refer to SOM's detailed pages for specific additional information.

The following interfaces are ordered by routing priority, meaning that (by default, for the full feature set of the interface) the signal integrity of the former is more critical than the latter.

PCI Express

PCB

Parameter for PCI Express Differential Pairs	Min	Typ	Max
Differential Impedance [Ohm]	-	100	-
Common Mode Impedance [Ohm]	-	60	-
Gap than other signals (reccomended)	-	2xgap	-
Intra pair matching [mils]*	-	-	10
Max Total Length [in]*	-	-	12
Maximum allowed stub	-	-	0
Max allowed vias	-	-	6

• * Including SoM trace length
• Preferred underneath plane over entire trace length GND.

USB 3.0

Schematics

• Create schematic in accordance with DAVE Embedded Systems system-on-modules (SOM) USB specification ( see SOM detailed pages )

PCB

Parameter for USB Differential Pairs	Min	Typ	Max
Differential Impedance(ohm)	80	90	100
Common Mode Impedance	40,5	45	49.5
Gap than other signals	3xgap	5xgap	-
Intra pair matching(mils)	0	25	150
Max allowed stubs	-	-	0
Max traces length	-	-	note 1
Max allowed plane split under traces	-	-	0

note 1 see SOM detailed specifications

• If a stub is unavoidable in the design, no stub should be greater than 200 mils.
• Place a continuos reference plane underneath differential pair

SATA

Schematics

• Use certified SATA connector

PCB

Parameter for SATA Differential Pairs	Min	Typ	Max
Differential Impedance(ohm)	80	100	120
Common Mode Impedance(ohm)	51	60	69
Gap than other signals	2xgap	-	-
Intra pair matching(mils	-	-	note 1
Inter pair matching(mils)	-	-	note 1
Max allowed stubs	-	-	0
Max allowed plane split under traces	-	-	0
Max allowed length	-	-	note 1

note 1 see SOM detailed specifications

• Place a continuos reference plane underneath differential pair
• Minimized vias use
• No strong matching required between TX and RX, but keep same route for every differential pair

Ethernet 10/100/1000

Case #1: PHY is integrated on SOM

This section refers to the case of PHY integrated on SOM such as Lizard and MAYA.

Schematics

• If LAN connector with integrated magnetic is used:
  • predispose ethernet protection diodes on ethernet lines
  • Connect connector shield to an adeguate GND or shield Plane

PCB

Refer to this table for 10/100 differential pairs routing

Parameter for 10/100 differential pair	Min	Typ	Max
Differential Impedance(ohm)	-	100	-
Common Mode Impedance	-	50	-
Gap than TX and RX signals	2xgap	2xgap	-
Gap than other signals	2xgap	4xgap	-
Intra pair matching(mils)*	0	25	150
TX and RX via # mismatch*	0	0	1

Refer to this table for Gigabit differential pairs routing

Parameter for Gigabit Differential Pairs	Min	Typ	Max
Differential Impedance(ohm)	-	100	-
Common Mode Impedance	-	50	-
Gap than TX and RX signals	2xgap	2xgap	-
Gap than other signals	2xgap	4xgap	-
Intra pair matching(mils)*	0	10	10
Max PCB trace length	3"	5"	-
TX and RX via # mismatch*	0	0	1

* Not mandatory but recommended.

• If LAN connector with integrated magnetic is used:
  • do not route traces under the connettor, neither on opposite side
  • place filter diode near connector
  • place others signals far from connector
  • Connect connector shield to an adeguate GND or shield Plane or Copper through numerous vias
• If on board magnetic are used
  • adeguately isolate system GND from magnetic connector side
  • Connect connector shield to an adeguate GND or shield Plane or Copper through numerous vias if necessary
• try to match as best as possible each differential pair (intrapair matching)
• Keep as best as possibile the same route for TX and RX traces
• If less than minimum gap is used, use a GND trace for improve trace separation

Case #2: PHY is not integrated on SOM and a RGMII PHY is used

This section refers to the case of:

• PHY not integrated on SOM
• Gigabit PHY populated on carrier board and connected to SOM through RGMII interface.

This solution is implemented on NaonEVB-Mid for example.

Schematics

• Add series resistors (RPACK resistors recommended) to RGMII lines
• Properly decouple PHY Power Supplies rails
• Properly decouple every supply pin of Ethernet PHY
• Properly separate analog Supply Rails

PCB

Parameter for RGMII interface	Min	Typ	Max
Common mode impedance(ohm)	-	50	-
Gap than other ethernet diff pair	4xwidth	-	-
Gap than other signals	4xwidth		-
Matching(mils)	-	-	200
Via Mismatch	0	0	1

Parameter for Gigabit Differential Pairs	Min	Typ	Max
Differential Impedance(ohm)	-	100	-
Common Mode Impedance	-	50	-
Gap than TX and RX signals	2xgap	2xgap	-
Gap than other signals	2xgap	4xgap	-
Intra pair matching(mils)	0	10	10
Max PCB trace length	3"	5"	-
TX and RX via # mismatch*	0	0	1

* Not mandatory but recommended.

• Ground and VCC planes must be as large as possible
• Avoid plane split and voids
• Place bypass capacitor near every PHY supply pin
• Connect every capacitor's pin to the plane with at least 2 vias and the shortest trace pattern
• Place PHY device at least 1" (25mm) distance far away from connector
• Keep MDIO clock signal isolated from other signals

Case #3: PHY is not integrated on SOM and a RMII PHY is used

This section refers to the case of

• PHY not integrated on SOM
• 10/100 Ethernet PHY populate don carrier board and interfaced to SOM through RMII interface.

This solution is implemented for example in MayaEVB-Lite board.

Schematics

• If possible, place series resistor to RMII interface signals
• Properly decouple PHY Power Supplies rails
• Properly separate analog Supply Rails
• Properly decouple every supply pin of Ethernet PHY
• Use a standard RMII PHY that supports correct clock mode (see SOM specification for further details)

PCB

Parameter for RMII interface	Min	Typ	Max
Reccomended Common mode impedance(ohm)	-	50	-
Gap between other signal	2xW		-

• Since RMII signals are not critical such as RGMII, is not necessary a strong matching between signal
• Avoid use of long traces
• Avoid stubs
• Keep as best as possibile the same routing for all RMII traces

Parameter for Ethernet Differential Pairs	Min	Typ	Max
Differential Impedance(ohm)	-	100	-
Common Mode Impedance	-	50	-
Gap than other TX and RX signals	2xgap	2xgap	-
Gap than other signals	2xgap	4xgap	-
Intra pair matching(mils)*	0	25	150
TX and RX via # mismatch*	0	0	1

* Not mandatory but recommended.

• Ground and VCC planes must be as large as possible
• Avoid plane split and voids
• Place bypass capacitor near every PHY supply pin
• Connect every capacitor's pin to the plane with at least 2 vias and the shortest trace pattern
• Place PHY device at least 1" (25mm) distance far away connector
• Keep MDIO clock signal isolated from other signals

HDMI

Schematics

• Add a Transmitter Port Protection to HDMI lines
• Use certified HDMI connector
• Connector shield must be properly connected

PCB

Parameter for HDMI Differential Pairs	Min	Typ	Max
Differential Impedance(ohm)	85	100	115
Gap than other signals	3xgap	5xgap	-
Intra pair matching(mils) at 225MHz clock	0	20	250
Inter pair matching(mils) at 225MHz clock	0	250	1"
Max allowed stubs	-	-	0
Max allowed plane split under traces	-	-	0

• Place a continuos reference plane underneath differential pair
• Try to match lines as best as possible

LVDS

PCB

Parameter for LVDS Differential Pairs	Min	Typ	Max
Differential Impedance [Ohm]	85	100	115
Common Mode Impedance [Ohm]	46.75	55	63.25
Gap than other signals (reccomended)	-	2xgap	-
Intra pair skew [mils]*	-	-	5
Inter pair skew [mils]**	-	400	-
Maximum allowed stub	-	-	0

• Prefer to route traces on TOP layer, referring them to a continuos GND plane.
• * Not includes SOM's length.
• ** Typical value can be relaxed depending on LVDS clock frequency

USB 2.0

Schematics

• Create schematic in accordance with DAVE Embedded Systems system-on-modules (SOM) USB specification ( see SOM detailed pages )

PCB

Parameter for USB Differential Pairs	Min	Typ	Max
Differential Impedance(ohm)	80	90	100
Common Mode Impedance	40,5	45	49.5
Gap than other signals	3xgap	5xgap	-
Intra pair matching(mils)	0	25	150
Max allowed stubs	-	-	0
Max traces length	-	-	note 1
Max allowed plane split under traces	-	-	0

note 1 see SOM detailed specifications

• If a stub is unavoidable in the design, no stub should be greater than 200 mils.
• Place a continuos reference plane underneath differential pair

SD/MMC/SDIO Interface

	Min	Typ	Max
Common Mode impedance SOM(ohm)	-	50	60
Matching required*	-	-	-
Max allowed parallel routing(mils)	-	-	1000
Max trace Length**	-	-	-
Max # of vias allowed	-	-	-

*This is not mandatory, however it is suggested in case trace length exceeds 10cm

**Overall trace length - i.e. Bora + carrier board - should not exceed 10cm. If this is not possible, try to avoid parallel routing in order to reduce crosstalk, and refer them to a ground plane.

LCD Interface

Schematics

• Please refer to DAVE Embedded Systems system-on-modules (SOM) carrier board documentationfor further information
• Predispose series resistor terminator (RPACK for LCD data and single resistor for Clock and H-SYNC and V-SYNC)
• Series resistor value may vary depending by PCB and schematic

PCB

• If possible, use 50ohm common mode lines
• Match LCD parallel signals in accordance with Pixel Clock frequency (further details in SOM specifications)
• Avoid use of long traces connection (max 10" on PCB)
• Avoid stubs

VIN Interface

Schematics

• Please refer to DAVE Embedded Systems system-on-modules (SOM) carrier board documentation for further information
• Predispose series resistor terminator (RPACK for LCD data and single resistor for Clock and H-SYNC and V-SYNC)
• Series resistor value may vary depending PCB and schematic

PCB

• If possible, use 50ohm common mode lines
• Match VIN parallel signals in accordance with Pixel Clock frequency (further details in SOM specifications)
• Avoid use of long traces connection (max 10" on PCB)
• Avoid stubs

I2C Interface

Schematics

• Predispose properly pullup resistors on line in accordance with DAVE Embedded Systems system-on-modules (SOM)
• Do not overload I2C lines with too much devices
• Ensure that I2C devices are being properly initialized during power up

PCB

• Isolate I2C clock from noise sensitive signals
• Avoid stub

CAN Interface

	Min	Typ	Max
Differential Mode impedance(ohm)	108	120	132
Matching required	-	-	-
Min Interpair spacing	-	4xgap	-
Max allowed parallel routing(mils)	-	-	-
Max trace Length	-	-	-
Max via allowed	-	-	-

Functional guidelines

Sudden power off management

From the architectural standpoint, modern embedded systems often resemble traditional PCs. For example:

• they implement a rich set of I/O interfaces (large displays, Ethernet ports, USB ports, SDIO sockets etc.)
• they likely run complex operating systems that derive from desktop world (Linux, Android, Windows CE etc.)
• they implement complex storage schemes (raw NAND, SSD, eMMC etc.).

One of the main differences between such systems and PCs is that the formers are - if appropriately designed - inherently resilient to sudden power fails. In any case, system designer should take into account these events and decide if and how to manage them explicitly. Here are some typical techniques used to deal with this situation:

• in case the system is used by human operators, the use of clean shutdown - triggered by the user himself - should be encouraged to prevent sudden power off. Technically speaking, this can be done via GUI (soft button) or mechanical device (push buttons and alike). In the latter case, push-button controllers such as Linear LTC2954 can be very useful to implement this feature
• in case no human operators interact with the system, more complex solutions might be required. This strategy is strongly dependent on hardware characteristics of SOM and must be approached on a case-by-case basis.

Thermal Management

Heat is generated by all semiconductors while operating and is dissipated to the surrounding environment. This amount of heat is a function of the power consumed and the thermal resistance of the device package. Every silicon device on an electronic board must operate within the limits of its operating temperature parameters (eg, the junction temperature) as specified by the silicon vendor.

Failure to maintain the temperature within safe ranges reduces operating lifetime, reliability, and performance and may cause irreversible damage to the system. Therefore, the product design cycle should include thermal analysis to verify that the device works within its functional limits. If the temperature is too high, component or system-level thermal enhancements are required to dissipate the heat from the system.