BELK-TN-007: FreeRTOS on single-core Bora Lite SoM

From DAVE Developer's Wiki
Jump to: navigation, search
Info Box
Bora5-small.jpg Applies to Bora
BORA Xpress.png Applies to BORA Xpress
BORALite-TOP.png Applies to BORA Lite


Warning-icon.png This technical note was validated against specific versions of hardware and software. What is described here may not work with other versions. Warning-icon.png

History[edit | edit source]

Version Date Notes
1.0.0 February 2020 First public release

Introduction[edit | edit source]

In general, Bora Lite SoM is suited for compact, cost-sensitive applications for which Bora or BoraX would be overkilling. In this scenario, Bora Lite is often equipped with XC7Z007 or XC7Z014 SoC's, which implement single-core processors. In combination with FreeRTOS, such configurations can be the right solution to address real-time applications not requiring the rich set of features provided by GNU/Linux operating system. This Technical Note (TN) describes how to run a FreeRTOS Hello, world!-type application a single-core Bora Lite model.

Testbed[edit | edit source]

From the hardware perspective, the testbed is like the one shown here. It consists of a BoraXEVB carrier board, a Bora Lite Adapter, and a single-core Bora Lite SoM (equipped with XC7Z007 SoC).

The BoraXEVB carrier board is set up to make the SoM boot from the microSD card.

As bootloader, the U-Boot release provided by the BELK kit is used:

U-Boot SPL 2017.01-belk-4.1.1 (Jan 08 2020 - 16:46:11)
mmc boot
Trying to boot from MMC1
reading fpga.bit
spl_load_image_fat: error reading image fpga.bit, err - -1
spl: error reading image fpga.bit, err - 1
reading u-boot.img
reading u-boot.img


U-Boot 2017.01-belk-4.1.1 (Jan 08 2020 - 16:46:11 +0100), Build: belk-4.1.1

Model: Bora
Board: Xilinx Zynq
I2C:   ready
DRAM:  ECC disabled 1 GiB
Relocating to 3ff14000, new gd at 3ead3ee8, sp at 3ead3ec0
NAND:  1024 MiB
MMC:   sdhci@e0100000: 0 (SD)
reading bora.env
In:    serial@e0001000
Out:   serial@e0001000
Err:   serial@e0001000
Model: Bora
Board: Xilinx Zynq
SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 32 MiB
SOM ConfigID CRC mismatch for 0xff0101ff (was 0xffffffff, expected 0xca9a6d16) at block 2 (offset 96): using default
SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 32 MiB
SOM UniqueID not found, using default
SOM ConfigID#: ffffffff
SOM UniqueID#: ffffffff:ffffffff
ds2431_readmem(): error in chip reset
ds2431_readmem(): error in reading buffer
ds2431_readmem(): error in chip reset
ds2431_readmem(): error in reading buffer
CB ConfigID CRC mismatch for 0x00000000 (was 0x00000000, expected 0x2144df1c) at block 3 (offset 96): using default
CB ConfigID#: ffffffff
CB UniqueID#: 00000000:00000000
Net:   ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id
eth0: ethernet@e000b000
Bora>

The procedure described in this TN makes use of the Xilinx SDK (XSDK) too. Specifically, the version 2019.1 running on a Windows PC was used.

Setting up the Hello, world! project[edit | edit source]

This section illustrates how to set up the software project. As an example, the classical Hello, world!-type application was used.

The first step is to create a new Application Project:

Crating the Application Project


Regarding the Hardware Platform, a new one has to be created. To do that, a hardware specification file needs to be imported as shown in the following screenshot. In this example, the hardware specification file used is associated with the basic Vivado project delivered along with the BELK kit.

Creating a new hardware platform


Please configure the remaining parameters as illustrated here:

Setting up Application project parameters


Then select the FreeRTOS Hello World template:

Selecting the FreeRTOS Hello World template


Once the creation process is completed, you should see three different "projects" on the left (one is the real application project, one is the FreeRTOS BSP, and one is associated with the imported hardware platform).

Three projects are created


In order to route the serial console to the UART1, please click on Modify this BSP's settings button and change stdin and stdout parameter as shown below:

Changing stdin and stdout parameters


Select the Clean item from the Project menu:

Cleaning all the the projects (1/2)
Cleaning all the projects (2/2)


By default, the cleaning process will trigger the build process as well. Once the build process in finished, the application executable is ready to be deployed on the target.

Running the application[edit | edit source]

There are several ways to run the application on the target. For instance, a JTAG debugging tool can be used. The following is a script in PRACTICE language used to set up a debugging session with Lauterbach TRACE32 PowerView:

	SYStem.CPU ZYNQ-7000CORE0
	
	
	; This selects the DAP for accessing the ARM cores 
	; (accessing the TAP of the FPGA logic requires different settings)
	SYStem.CONFIG DAPIRPRE 6.      
	SYStem.CONFIG DAPIRPOST 0.
	SYStem.CONFIG DAPDRPRE 1.
	SYStem.CONFIG DAPDRPOST 0.
	
	TRONCHIP.SET UNDEF OFF
	TRONCHIP.SET DABORT OFF
	TRONCHIP.SET PABORT OFF
	SYStem.Option DACR ON 
	
	SYStem.OPTION MMU ON
	SYStem.OPTION MMUSPACES OFF ; linux is not started yet!
	;enddo
	; run bootrom and FSBL to init the whole system
	;SYStem.UP
	; go is disabled because reset is not connected and UP act like a attach
	;go
	system.mode attach

	break
    break.delete /all
    
	TASK.CONFIG ~~/demo/arm/kernel/freertos/freertos.t32       ; load FreeRTOS awareness
	MENU.ReProgram ~~/demo/arm/kernel/freertos/freertos.men    ; load FreeRTOS menu

	data.load.elf r:\home\dvdk\devel\boralite\workspace-2019.1\freertos_hello_world\Debug\freertos_hello_world.elf

	b.s main
	
	go
	enddo


Please note that the FreeRTOS console is routed to the same UART used for the U-Boot console:

Debugging session with Lauterbach TRACE32 PowerView


Another way to download and run the application is by using the tftpboot and bootelf commands as shown in the following example (*):

Bora> tftpboot ${loadaddr} boralite/freertos_hello_world.elf
Using ethernet@e000b000 device
TFTP from server 192.168.0.13; our IP address is 192.168.0.81
Filename 'boralite/freertos_hello_world.elf'.
Load address: 0x2080000
Loading: #################################################################
         #########################
         1.4 MiB/s
done
Bytes transferred = 457608 (6fb88 hex)
Bora> bootelf 0x2080000
CACHE: Misaligned operation at range [00100000, 0010e78c]
CACHE: Misaligned operation at range [0010e78c, 0010e798]
CACHE: Misaligned operation at range [0010e798, 0010e7a4]
CACHE: Misaligned operation at range [0010e7a8, 0010ef84]
CACHE: Misaligned operation at range [0010ef88, 0010fcbc]
CACHE: Misaligned operation at range [0010fcbc, 0010fcc0]
CACHE: Misaligned operation at range [00114000, 00114008]
CACHE: Misaligned operation at range [00114008, 0011400c]
CACHE: Misaligned operation at range [0011400c, 00114010]
CACHE: Misaligned operation at range [00114010, 00124554]
CACHE: Misaligned operation at range [00124554, 00126560]
CACHE: Misaligned operation at range [00126560, 00129d60]
## Starting application at 0x00100000 ...
Hello from Freertos example main
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
FreeRTOS Hello World Example PASSED


(*) It seems that the message CACHE: Misaligned operation at range [x, y] is not a real problem.

Related links[edit | edit source]