Creating and building example Vivado project (BELK/BXELK)


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Applies to Bora

Applies to BORA Xpress

In this document, the Vivado installtion path may be indicated as vivado_201x.y. Just replace x and y with the actual numbers of your version. For instance, use the string vivado_2014.4 if you are working with Vivado 2014.4.

History

Version	Date	BELK version	Notes
1.0.0	November 2015	3.0.0	First release
2.0.0	July 2017	3.0.0, 4.0.0	Updates for BELK 4.0.0 / BXELK 2.0.0

Introduction

BELK/BXELK provides an example Vivado project for BORA/BORAX boards. This project allows to:

generate FSBL binary image
generate the bitstream of a simple PL design used to route PS' CAN0 and UART0 signals through EMIO (see also the following pictures).

Block diagram of BORA example project

Block diagram of BORAX example project

This article describes how two build this project. Two procedures are described, the former is command line based while the latter is GUI based.

The project is stored is a git repository, as described here.

It is assumed that the Zynq development environment has been set up properly (see this page for more details).

Command line based procedure

The following procedure is detailed for Bora board. For BoraX board please replace:

bora_FSBL with borax_FSBL
bora_wrapper_hw_platform_0 with borax_wrapper_hw_platform_0
bora.sdk with borax.sdk
bora_wrapper.bit with borax_wrapper.bit.

start the Zynq development server and login into the system
assuming that a local repository has not been created, clone the remote BORA git repository:
git clone git@git.dave.eu:dave/bora/bora.git
copy the <bora_repo>/boards/ directory to <vivado_install_dir>/data/boards/ :

cd <bora_repo>
sudo cp -r boards/ /opt/Xilinx/Vivado/<Vivado_version>/data/

enter the git directory and launch the following command to set the project directory
export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk
launch the Vivado Design Suite with the following commands^[a]^[b]:

. /opt/Xilinx/Vivado/<Vivado_version>/settings64.sh
vivado -mode tcl -source build_project.tcl -notrace -tclargs "-bitstream"

the build_project script allows user to select BORA or BORAX target
at the end of the bitstream build process, the build_project script allows to automatically export hardware and lauch SDK to build the FSBL.
For BELK 3.0.2 or older and for BXELK 1.0.1 or older: please follow the FSBL build instructions
For BELK 4.0.0 or newer and BXELK 2.0.0 or newer, by default FSBL is not used anymore in the boot process. U-Boot SPL (first-stage bootloader) is used instead. PS configuration files are used to build U-boot binaries.
- Copy the ps7_init_gpl.c and ps7_init_gpl.h source files into U-boot source code directory using the following command example for Bora:

cp $PROJ_DIR/bora.srcs/sources_1/bd/bora/ip/bora_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/bora/

Follow U-boot build instructions to build U-boot using new PS configurations (please note that Default BELK/BXELK PS configuration is already used by default in U-boot release)

GUI based procedure

The following procedure is detailed for Bora board. For BoraX board please replace:

bora_wrapper.v with borax_wrapper.v
bora_pinout.xdc with borax_pinout.xdc
bora_timings.xdc with borax_timings.xdc
bora_FSBL with borax_FSBL
bora.sdk with borax.sdk
bora_FSBL.elf with <code>borax_FSBL.elf
bora_wrapper.bit with borax_wrapper.bit.

start the Zynq development server and login into the system
assuming that a local repository has not been created, clone the remote BORA git repository:git clone git@git.dave.eu:dave/bora/bora.git

copy the <bora_repo>/boards/ directory to <vivado_install_dir>/data/boards/ :

cd <bora_repo>
sudo cp -r boards/ /opt/Xilinx/Vivado/<Vivado_version>/data/

launch the Vivado Design Suite GUI with the following commands^[c]:

. /opt/Xilinx/Vivado/201x.y/settings64.sh
vivado

from the start page click on Create New Project
click Next
select the directory build project, insert the name of the project Project Name and click Next
select RTL Project, enable Do not specify sources at this time and click Next
on the Default Part form, click on the Boards button to filter the available boards. Select BORA or BORAX depending on target SOM and click Next
check the summary page and click Finish
in the Vivado GUI click on Create Block Design from the Flow Navigator
insert bora (or borax in case of BoraX board) as Design name and click OK
this creates a new block design. From the Diagram tab, add a new IP:
- click the Add IP side button, or
- click Add IP on the upper suggestions bar
double click on ZYNQ7 Processing System
this adds the IP that models the PL component of Zynq. Launch Run Block Automation from the upper suggestions bar
check that Apply Board Preset is selected and click OK
this applies the default settings for BORA/BORAX and creates the I/O ports for the DDR and MIO pins
- for BELK <= 3.0.2 and BXELK <= 1.0.1: the default settings automatically creates also connections for the UART_0 and CAN_0 interfaces
- for BELK-4.0.0 and BXELK-2.0.0: UART_0 and CAN_0 connections must be manually created:
  - right-clicking on each port (where mouse cursor switch to pencil) and selecting Make External or with keyboard shortcut Ctrl+T. The name of the external ports must be UART_0 and CAN_0 respectively, otherwise correct manually
  - alternatively, execute the following commands from tcl console:

create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART_0
connect_bd_intf_net [get_bd_intf_pins /[get_bd_cells]/UART_0] [get_bd_intf_ports UART_0]
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:can_rtl:1.0 CAN_0
connect_bd_intf_net [get_bd_intf_pins /[get_bd_cells]/CAN_0] [get_bd_intf_ports CAN_0]

manually connect the FCLK_CLK0 signal to M_AXI_GP0_ACLK and save the block design
from the sources tab, select the BORA/BORAX block design (bora.bd for Bora, borax.bd for BoraX) as Design Sources and from the context menu select Create HDL Wrapper
on the next window, select Copy generated wrapper to allow user edits and click OK
this creates the Verilog file (bora_wrapper.v for Bora, borax_wrapper.v for BoraX). If this file is not automatically included in the project, add it using the Add sources option
- select Add or create design sources and click Next
- select the bora_wrapper.v file from the <prj_name>.srcs/sources_1/bd/bora/hdl/ directory
select Add sources and click on Add or create constraints
select the bora_pinout.xdc and bora_timings.xdc files from the constr directory of the BORA repository
check that the option Copy constraints files into project is enabled
create the synthesis, implementation and bitstream clicking Generate Bitstream from the Flow Navigator and wait the completion of the operation
once completed, select Open Implemented Design
create the binary bitstream running the tcl script provided with the BORA repository. Launch Tools -> Run Tcl Script
select the generate_binary_bitstream.tcl file from the scripts directory from the BORA repository
select File -> Export -> Export Hardware
on the next window, enable Include Bitstream and click OK
now launch the SDK session to generate the FSBL, clicking on File -> Launch SDK
For BELK <= 3.0.2 and BXELK <= 1.0.1 : please follow the FSBL build instructions
For BELK-4.0.0 and BXELK-2.0.0 there is no need to build FSBL. Instead PS configurations files are used to build U-boot binaries.
- Copy the ps7_init_gpl.c and ps7_init_gpl.h source files into U-boot source code directory using the following command example for Bora:

cp $PROJ_DIR/bora.srcs/sources_1/bd/bora/ip/bora_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/bora/

Follow U-boot build instructions to build U-boot using new PS configurations (please note that Default BELK/BXELK PS configuration is already used by default in U-boot release)

↑ In a 32 bit system, Vivado settings are configured with the following command /opt/Xilinx/Vivado/<Vivado_version>/settings32.sh
↑ Passing the -tclargs "-bitstream" parameters allows for automatic building of the FPGA bitstream.
↑ In a 32 bit system, Vivado settings are configured with the following command /opt/Xilinx/Vivado/201x.y/settings32.sh

FSBL project build

once the Xilinx SDK is ready, perform the following operations from the GUI:
- Click on File -> New -> Application Project
- select the Project Name: bora_FSBL
- Click Next
- Select Template: Zynq FSBL
- Click on Finish
- apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply Patch..
from Browse... open the file <bora_repo>/patch/belk-sd-boot.patch
- Click Next
- Select Apply the patch to the selected file, folder or project: and select main.c from bora_FSBL -> src
- Click Next
- Check that the patch is correctly applied to the source code and click on Finish
- Vivado v2014.4 only: With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):
  - apply <bora_repo>/patch/AR65145_ps7_init_c.patch on ps7_init.c under bora_wrapper_hw_platform_0
  - apply <bora_repo>/patch/AR65145_ps7_init_tcl.patch on ps7_init.tcl under bora_wrapper_hw_platform_0
the FSBL (ELF file) is built automatically
create the binary from the FSBL ELF chosing one of the following options:
- manually launch the command: arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin
this step is board dependent
- configure the automatic binary generation on project build. In Project Explorer, right-click on bora_FSBL project and select C/C++ Build Settings and add the command arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin on Post-build steps
create the BOOT.bin image (single file including FSBL, FPGA and U-boot for uSD boot):
- select the bora_FSBL project in Project Explorer
- click on Xilinx Tools -> Create Zynq Boot Image
if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add U-Boot to the list.
otherwise, select Create new BIF file and set the output path and in Boot image partitions add the following files:
- bora_FSBL.elf, which can be found in the project Debug directory. N.B. check that the Partition Type for FSBL is bootloader
  - bora_wrapper.bit, which is the bitstream generated by the Vivado project (Partition Type must be Datafile)
- u-boot.elf, which is the compiled U-Boot with .elf extension (Partition Type must be Datafile)
in Output path, select the path for the BOOT.bin file

Helloworld from UART0

Using the FPGA bitstream previously created, it is possible to use serial tty port on Linux. The serial port is mapped to /dev/ttyPS1 (this is because /dev/ttyPS0 is the console mapped to UART1).

Here below an example on C code for initializing and using UART0 through FPGA:

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <fcntl.h> 
#include <termios.h>

int set_interface_attribs (int fd, int speed, int parity)
{
        struct termios tty;
        memset (&tty, 0, sizeof tty);
        if (tcgetattr (fd, &tty) != 0)
        {
                printf("error %d from tcgetattr", errno);
                return -1;
        }

        cfsetospeed (&tty, speed);
        cfsetispeed (&tty, speed);

        tty.c_cflag = (tty.c_cflag & ~CSIZE) | CS8;     // 8-bit chars
        // disable IGNBRK for mismatched speed tests; otherwise receive break
        // as \000 chars
        tty.c_iflag &= ~IGNBRK;         // disable break processing
        tty.c_lflag = 0;                // no signaling chars, no echo,
                                        // no canonical processing
        tty.c_oflag = 0;                // no remapping, no delays
        tty.c_cc[VMIN]  = 0;            // read doesn't block
        tty.c_cc[VTIME] = 5;            // 0.5 seconds read timeout

        tty.c_iflag &= ~(IXON | IXOFF | IXANY); // shut off xon/xoff ctrl

        tty.c_cflag |= (CLOCAL | CREAD);// ignore modem controls,
                                        // enable reading
        tty.c_cflag &= ~(PARENB | PARODD);      // shut off parity
        tty.c_cflag |= parity;
        tty.c_cflag &= ~CSTOPB;
        tty.c_cflag &= ~CRTSCTS;

        if (tcsetattr (fd, TCSANOW, &tty) != 0)
        {
                printf("error %d from tcsetattr", errno);
                return -1;
        }
        return 0;
} 


int main()
{
	int fd;
	char *portname = "/dev/ttyPS1";

	char msg[] = "Hello World from BELK (FPGA PS0 UART)!\n\r";

	fd = open(portname, O_RDWR | O_NOCTTY | O_SYNC);
	if (fd < 0)
	{
        	printf("error %d opening %s: %s", errno, portname, strerror (errno));
	        exit(1);
	}
	printf(msg);

	set_interface_attribs (fd, B115200, 0);  // set speed to 115,200 bps, 8n1 (no parity)
	write(fd, msg, strlen(msg));

	exit(0);
}

and then compile it:

dvdk@vagrant-ubuntu-trusty-64:~/bora/rfs/belk/home/root$ $CC hello_UART0.c -o hello_UART0

The program executed print out the msg string on serial console and on /dev/ttyPS1 port.

[1] In a 32 bit system, Vivado settings are configured with the following command /opt/Xilinx/Vivado/<Vivado_version>/settings32.sh

[2] Passing the -tclargs "-bitstream" parameters allows for automatic building of the FPGA bitstream.

[3] In a 32 bit system, Vivado settings are configured with the following command /opt/Xilinx/Vivado/201x.y/settings32.sh

[a]

[b]

[c]

Creating and building example Vivado project (BELK/BXELK)

Contents

History

Introduction

Command line based procedure

GUI based procedure

FSBL project build

Helloworld from UART0

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