BELK-AN-004: Interfacing BoraEVB/BoraXEVB to TFT LCD display
Info Box
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This application note was validated against specific versions of the kit only. It may not work with other versions. Supported versions are listed in the History section. | ![]() |
It is assumed to use ZYNQ SOC with speed grade -1 (even using command line script or GUI). In any case, there are no issues using speed grade -3 SOC provided with BELK kit |
Contents
History[edit | edit source]
Version | Date | BELK/BXELK version | Notes |
---|---|---|---|
1.0.0 | September 2015 | 2.2.0 | First release |
2.0.0 | November 2015 | 2.2.0, 3.0.0 | Added support for BoraX/BoraXEVB platform |
March 2017 | 2.2.0, 3.0.0 | Added info for installing Qt on rfs using smart
| |
3.0.0 | January 2020 | 4.1.0 / 2.1.0 | AN migration to BELK 4.1.0 / BXELK 2.1.0 |
Introduction[edit | edit source]
This application note describes the interfacing of Ampire AM-800480STMQW-TA1 display to BoraEVB and BoraXEVB. Main characteristics of this 7" TFT LCD panel are:
- 800x480 resolution
- color depth: 18 bpp
- electrical interface: LVDS (3 pairs).
Please, refer to the History table for using the proper BELK version used on the AN.
Physical interfacing[edit | edit source]
BoraEVB[edit | edit source]
To interface the display a small adapter board is needed. It interfaces J22 connector on BoraEVB side and provides a 20-pin connector to directly attach display cable.
The adapter board
- is also equipped with a linear regulator generating 2.5V. This voltage is used as power supply for the VDDIO_BANK13 rail. This voltage is required to implement LVDS differential pairs that drive display.
- integrates a pad (denoted as TP1) that is used to connect 5V power supply generated by MOD2 PSU of BoraEVB. This additional power rails is required by display backlight circuitry.
Ampire AM-800480STMQW-TA1 part integrates resistive touch too. This is directly connected to BoraEVB's J25 connector. Resistive touch is managed by Texas Instruments TSC2003 controller (U27).
Schematics of adapter board can be downloaded from this link.
BoraXEVB[edit | edit source]
In case of BoraXEVB, no adapter board is needed. LCD panel is directly connected to J26 connector where PL bank 13's signals implementing LVDS interface are routed (see page 14 of the schematics). I/O voltage of bank 13 is set to 2.5V by configuring JP25 as shown in the following table.
Pins | Setting |
---|---|
1-2 | closed |
3-4 | open |
5-6 | closed |
7-8 | open |
9-10 | open |
11-12 | open |
Block diagram and Vivado project[edit | edit source]
The following pictures show simplified block diagram of the design.
LCD is driven by a controller implemented in PL that fetches pixel data from frame buffer and periodically refreshes physical screen. The LCD controller is composed of an AXI VDMA IP, the LCD controller itself and a parallel-to-LVDS serializer. AXI VDMA and the LCD controller provides configuration registers that are mapped in the following address range:
- AXI VDMA: 0x43000000 - 0x4300FFFF
- LCD Controller: 0x43C00000 - 0x43C0FFFF
The following picture shows the block diagram of the Vivado project with LCD controller:
To implement frame buffer, a portion of main SDRAM is used. This area is allocated at runtime by linux frame buffer driver. Even if LCD is 18 bpp, each pixel is represented by 32-bit word in memory. In fact each pixel is in RGB666 format, so for each colour only the six most significant bits of the frame buffer RGB888 are used to drive the display.
The Vivado project can also be build with the procedure explained here.
Bora + BoraEVB[edit | edit source]
Here is the pinout assignment to drive the LCD:
LCD Signal | BORA SOM Signal |
BackLight (*) | IO_L15P_T2_DQS_13 |
LVDS_CLK_P | IO_L22P_T3_13 |
LVDS_CLK_N | IO_L22N_T3_13 |
LVDS_D0_P | IO_L21P_T3_DQS_13 |
LVDS_D0_N | IO_L21N_T3_DQS_13 |
LVDS_D1_P | IO_L19P_T3_13 |
LVDS_D1_N | IO_L19N_T3_VREF_13 |
LVDS_D2_P | IO_L18P_T2_13 |
LVDS_D2_N | IO_L18N_T2_13 |
(*) This signal is used to control backlight. It is usually driven by a PWM signal whose duty cycle is proportional to backlight intensity. For the sake of simplicity, in this project this signal is driven by a GPIO, thus only two intensity levels are supported (0% and 100%).
The Vivado project can also be build with the procedure explained here with the following modifications:
export BASE_NAME bora_LVDS
export U-BOOT_PS7_DIR bora
BoraLite + Adapter + BoraXEVB[edit | edit source]
Here is the pinout assignment to drive the LCD:
LCD Signal | BORA SOM Signal |
BackLight (*) | IO_L6N_T0_VREF_13 (**) |
LVDS_CLK_P | IO_L13P_T2_MRCC_13 (**) |
LVDS_CLK_N | IO_L13N_T2_MRCC_13 (**) |
LVDS_D0_P | IO_L12P_T1_MRCC_13 (**) |
LVDS_D0_N | IO_L12N_T1_MRCC_13 (**) |
LVDS_D1_P | IO_L15P_T2_DQS_13 (**) |
LVDS_D1_N | IO_L15N_T2_DQS_13 (**) |
LVDS_D2_P | IO_L11P_T1_SRCC_13 (**) |
LVDS_D2_N | IO_L11N_T1_SRCC_13 (**) |
(*) This signal is used to control backlight. It is usually driven by a PWM signal whose duty cycle is proportional to backlight intensity. For the sake of simplicity, in this project this signal is driven by a GPIO, thus only two intensity levels are supported (0% and 100%). This is a CMOS 2.5V level signal. Make sure that voltage levels of this signal are compatible with LCD backlight input.
(**) On the adapter this signal is routed (via configurable 0R) to multiple pins of the EVB connector to meet all the features of the EVB. Please make sure to configure the Adapter for the use of the LVDS connector.
The Vivado project can also be build with the procedure explained here with the following modifications:
export BASE_NAME boralite_LVDS
export U-BOOT_PS7_DIR bora
BoraLiteAdapter BLADP0000R0R[edit | edit source]
As the BoraLite SOM has fewer signals routed out as the other SOM, some signal are multiplexed via 0R resistors: the following table list these configurations:
Reference | PmodA conn. | LVDS conn. |
R33 | 0R | DNP |
R34 | 0R | DNP |
R35 | 0R | DNP |
R36 | 0R | DNP |
R37 | 0R | DNP |
R38 | 0R | DNP |
R39 | 0R | DNP |
R40 | x | DNP |
R41 | 0R | DNP |
R42 | x | 0R |
R43 | DNP | 0R |
R44 | DNP | 0R |
R45 | DNP | 0R |
R46 | DNP | 0R |
R47 | DNP | 0R |
R48 | DNP | 0R |
R49 | DNP | 0R |
R50 | DNP | 0R |
BoraX + BoraXEVB[edit | edit source]
Here is the pinout assignment to drive the LCD:
LCD Signal | BORA SOM Signal |
BackLight (*) | IO_0_13 |
LVDS_CLK_P | IO_L13P_T2_MRCC_13 |
LVDS_CLK_N | IO_L13N_T2_MRCC_13 |
LVDS_D0_P | IO_L12P_T1_MRCC_13 |
LVDS_D0_N | IO_L12N_T1_MRCC_13 |
LVDS_D1_P | IO_L14P_T2_SRCC_13 |
LVDS_D1_N | IO_L14N_T2_SRCC_13 |
LVDS_D2_P | IO_L11P_T1_SRCC_13 |
LVDS_D2_N | IO_L11N_T1_SRCC_13 |
(*) This signal is used to control backlight. It is usually driven by a PWM signal whose duty cycle is proportional to backlight intensity. For the sake of simplicity, in this project this signal is driven by a GPIO, thus only two intensity levels are supported (0% and 100%). This is a CMOS 2.5V level signal. Make sure that voltage levels of this signal are compatible with LCD backlight input.
The Vivado project can also be build with the procedure explained here with the following modifications:
export BASE_NAME borax_LVDS
export U-BOOT_PS7_DIR borax
Enabling frame buffer driver in linux kernel[edit | edit source]
U-boot:
- the default KIT binary files of u-boot (u-boot.img) and SPL (boot.bin) can be used.
- the variable
bootcmd
has to contain this string:video=borafb:800x480-32 cma=32M
- this can be achieved modifying the variable
addmisc
with the following command:
- this can be achieved modifying the variable
setenv addmisc 'setenv bootargs ${bootargs} ${mtdparts} video=borafb:800x480-32 cma=32M'
Kernel and device tree can also be built with the following procedure:
- update Bora kernel repository (as described here)
- the default KIT binary files of kernel (uImage) can be used.
- build the
bora-an004.dtb
devicetree
Put the binaries on the first (FAT32) partition of your BELK SD card, overwriting the original one if needed. Please note that you need the following files:
- boot.bin
- bora.dtb
- uImage
- fpga.bin
- u-boot.img
- uEnv.txt
Install root file system on second (ext4) partition of your BELK SD card (firstly deleting all previous rfs files):
- get rfs image here
Insert the SD card into Bora/BoraX EVB and turn on the board.
During kernel bootstrap, the following messages are printed out on console, indicating framebuffer driver has been loaded succesfully:
[ 0.600840] borafb borafb.0: fb0: Virtual frame buffer device, using 16384K of video memory @ phys 2d900000
You will also see two Tuxes on the top left corner of the LCD, indicating that this Linux system has two cores, as shown in the following picture:
Once the kernel has completed boot, frame buffer can be accessed from user space applications via /dev/fb0
device file (for more details please refer to https://www.kernel.org/doc/Documentation/fb/framebuffer.txt).
Pre-built binaries[edit | edit source]
- For Bora SoM use:
- For BoraLite SoM use:
- For BoraX SoM use:
How to install test tools for LCD device[edit | edit source]
- configure BELK for downloading new packages using
smart
: a useful description for using smart can be found here - configure network interface for accessing DAVE Yocto pre-built images. For example:
root@bora:~# ifconfig eth0 192.168.0.95 <-- BELK IP address root@bora:~# echo "nameserver 192.168.0.1" > /etc/resolv.conf <-- your DNS, otherwise select a public DNS like Google's one 8.8.8.8 root@bora:~# route add default gw 192.168.0.254 <-- your gateway address
- check network connectivity
root@bora:~# ping www.dave.eu PING www.dave.eu (147.123.240.198): 56 data bytes 64 bytes from 147.123.240.198: seq=0 ttl=49 time=72.510 ms
- add DAVE smart channel and update smart cache
root@bora:~# smart channel --add cortexa9hf_neon type=rpm-md baseurl=http://yocto.dave.eu/belk-4.1.0/cortexa9hf_neon/ root@bora:~# smart update
- install the
tslib
required packages usingsmart
root@bora:~# smart install tslib-calibrate-1.1-r0 ...
root@bora:~# smart install tslib-tests-1.1-r0 ...
root@bora:~# smart install fb-test-1.1.0-r0 ...
- calibrate resistive touchscreen
root@bora:~# ts_calibrate
touch on the 5 points displayed in sequence (4 corner + center)
- test the alignment of touchscreen
root@bora:~# ts_test
this tool allow to drag a point or to draw a line
- display some test patterns
root@bora:~# fb-test