General InformationEdit
ORCA Block DiagramEdit
ORCA TOP ViewEdit
ORCA BOTTOM ViewEdit
Processor and memory subsystemEdit
The heart of ORCA module is composed by the following components:
- i.MX8M Plus SoC application processor
- Power supply unit
- LPDDR4 memory bank
- eMMC or NAND flash banks
- Connectors:
- 1 x 260 pins SO-DIMM edge connector with interfaces signals
This chapter shortly describes the main ORCA components.
Processor InfoEdit
Processor | i.MX8M Plus Dual | i.MX8M Plus Quad |
# Cores | 2x Arm® Cortex®-A53 1x Arm® Cortex®-M7 1x Hi-Fi4 DSP |
4x Arm® Cortex®-A53 1x Arm® Cortex®-M7 1x Hi-Fi4 DSP |
Clock | 1.8 GHz | |
L2 Cache | 512 KB | |
LPDDR4 | 32 bit @ 2000 MHz (LPDDR4-4000) | |
GPU | 3D: Vivante GC 7000UL (2 Shader) 2D: Vivante GC520L OpenGL ES 3.1 | |
VPU | 1080p60 H.265, H.264, VP9, VP8 decoder 1080p60 H.265, H.264 encoder | |
NPU | 2.25 TOP/s Neural Processing Unit | |
Display Controller | Dual Channel LVDS up to 1080p60 | |
Video Output | 1x HDMI 2.0a 1x MIPI-DSI (4-lanes) | |
Camera Input | 2x MIPI CSI (4-lanes each) 2x ISP | |
Ethernet | 2x 10/100/1000 Mbit/s controller with AVB and IEEE1588 | |
PCIe | 1x PCIe 3 (1-lane) | |
USB | 2x USB 2.0/3.0 |
RAM memory bankEdit
LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:
CPU connection | Multi-mode DDR controller (MMDC) |
Size max | 8 GB |
Width | 32 bit |
Speed | 2000 MHz |
eMMC flash bankEdit
On board main storage memory eMMC is connected to the SDIO3 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:
CPU connection | SDIO3 |
Size min | 4 GB |
Size max | 64 GB |
Bootable | Yes |
NAND flash bankEdit
Section not completed yet |
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:
CPU connection | Raw NAND flash controller |
Page size | TBD |
Size min | TBD |
Size max | TBD |
Width | 8 bit |
Chip select | TBD |
Bootable | Yes |
Memory mapEdit
For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX8M Plus Applications Processor Reference Manual
Power supply unitEdit
ORCA embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
Hardware versioning and trackingEdit
ORCA SOM implements well established versioning and tracking mechanisms:
- PCB version is copper printed on PCB itself, as shown in Fig. 1
- serial number: it is printed on a white label, as shown in Fig. 2: see also Product serial number page for more details
- ConfigID: it is used by software running on the board for the identification of the product model/hardware configuration. For more details, please refer to this link
- On ORCA SOM ConfigID is stored on OTP memory
Part number compositionEdit
ORCA SOM module part number is identified by the following digit-code table:
Part number structure | Options | Description |
---|---|---|
Family | DMU | Family prefix code |
SOC |
|
Other versions can be available, please contact technical support |
RAM |
|
|
Storage eMMC/NAND/QSPI |
|
NAND SLC and eMMC are possible alternatives not available together. QSPI can be mounted or not. Other versions can be available, please contact technical support |
Mounting Options |
|
Other versions can be available, please contact technical support |
RFU |
|
|
Temperature range |
|
Other versions can be available, please contact technical support For the DAVE Embedded Systems' product Temperature Range classification, please find more information at the page Products Classification |
PCB revision |
|
PCB release may change for manufacturing purposes (i.e. text fixture adaptation) |
Manufacturing option |
|
typically connected to production process and quality |
Software Configuration |
|
If customers require custom SW deployed this section should be defined and agreed. Please contact technical support |
ExampleEdit
ORCA SOM code DMUA2300E0R-00
- DMU - ORCA SOM
- A - MIMX8ML8CVNKZAB (i.MX 8M Plus Quad - Quad Core, VPU, NPU, ISP, CAN-FD - 1.6 GHz - Industrial - Tj=-40/105°C)
- 2 - 4GB DDR4
- 3 - 8GB eMMC, No QSPI, No NAND
- 0 - EdgeLock SE050, 32.768K X2, Voltage monitor, SD1 interface @ 3V3
- 0 - RFU
- E - Extended grade: -20 to +85°C
- 0 - first version
- R - RoHS compliant
- -00 - MAC address only
Pinout TableEdit
Connectors and Pinout TableEdit
Connectors descriptionEdit
In the following table are described all available connectors integrated on ORCA SOM:
Connector name | Connector Type | Notes | Carrier board counterpart |
---|---|---|---|
J1 | SODIMM DDR4 edge connector 260 pin | TE Connectivity 2309407-1 |
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to ORCA pinout specifications. See the images below for reference:
Pinout table naming conventionsEdit
This chapter contains the pinout description of the ORCA module, grouped in two tables (odd and even pins) that report the pin mapping of the 260-pin DDR4 SO-DIMM ORCA connector.
Each row in the pinout tables contains the following information:
Pin | Reference to the connector pin |
Pin Name | Pin (signal) name on the ORCA connectors |
Internal connections |
Connections to the ORCA components
|
Ball/pin # | Component ball/pin number connected to signal |
Voltage | I/O voltage levels |
Type | Pin type:
|
Notes | Remarks on special pin characteristics |
Pin MUX alternative functions | Muxes:
The number of functions depends on platform |
Pinout Table ODD pins declarationEdit
Pin | Pin Name | Internal Connections | Ball/pin # | Voltage domain | Type | Notes | Alternative Functions | |
---|---|---|---|---|---|---|---|---|
J1.1 | DGND | DGND | - | - | G | |||
J1.3 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.5 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.7 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.9 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.11 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.13 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.15 | CPU_ONOFF | CPU.ONOFF | G22 | NVCC_SNVS_1V8 | I/O | internal pull-up 100k to NVCC_SNVS_1V8 | ||
J1.17 | CPU_PORn | CPU.POR_B
PMIC.POR_B |
J29
9 |
NVCC_SNVS_1V8 | I/O | internal pull-up 100k to NVCC_SNVS_1V8 | ||
J1.19 | PMIC_ON_REQ
//VMON_RST |
CPU.PMIC_ON_REQ
PMIC.PMIC_ON_REQ |
F22
39 |
NVCC_SNVS_1V8 | I/O | more information on Reset scheme page | ||
J1.21 | PMIC_RST_B | PMIC.PMIC_RST_B | 8 | NVCC_SNVS_1V8 | I/O | internal pull-up 100k to NVCC_SNVS_1V8 | ||
J1.23 | BOARD_PGOOD | MTR.RESET_B | 2 | NVCC_3V3 | O | |||
J1.25 | BOOT_MODE0 | CPU.BOOT_MODE0 | G10 | NVCC_3V3 | I | internal 10k pull-up or pull-down
according to specific model |
||
J1.27 | BOOT_MODE1 | CPU.BOOT_MODE1 | F8 | NVCC_3V3 | I | internal 10k pull-up or pull-down
according to specific model |
||
J1.29 | BOOT_MODE2 | CPU.BOOT_MODE2 | G8 | NVCC_3V3 | I | internal 10k pull-up or pull-down
according to specific model |
||
J1.31 | DGND | DGND | - | - | G | |||
J1.33 | LVDS0_D3_N | CPU.LVDS0_D3_N | J28 | - | D | |||
J1.35 | LVDS0_D3_P | CPU.LVDS0_D3_P | H29 | - | D | |||
J1.37 | LVDS0_D2_N | CPU.LVDS0_D2_N | H28 | - | D | |||
J1.39 | LVDS0_D2_P | CPU.LVDS0_D2_P | G29 | - | D | |||
J1.41 | LVDS0_CLK_N | CPU.LVDS0_CLK_N | G28 | - | D | |||
J1.43 | LVDS0_CLK_P | CPU.LVDS0_CLK_P | F29 | - | D | |||
J1.45 | LVDS0_D1_N | CPU.LVDS0_D1_N | F28 | - | D | |||
J1.47 | LVDS0_D1_P | CPU.LVDS0_D1_P | E29 | - | D | |||
J1.49 | LVDS0_D0_N | CPU.LVDS0_D0_N | E28 | - | D | |||
J1.51 | LVDS0_D0_P | CPU.LVDS0_D0_P | D29 | - | D | |||
J1.53 | DGND | DGND | - | - | G | |||
J1.55 | LVDS1_D3_N | CPU.LVDS1_D3_N | D28 | - | D | |||
J1.57 | LVDS1_D3_P | CPU.LVDS1_D3_P | C29 | - | D | |||
J1.59 | LVDS1_D2_N | CPU.LVDS1_D2_N | C28 | - | D | |||
J1.61 | LVDS1_D2_P | CPU.LVDS1_D2_P | B29 | - | D | |||
J1.63 | LVDS1_CLK_N | CPU.LVDS1_CLK_N | B28 | - | D | |||
J1.65 | LVDS1_CLK_P | CPU.LVDS1_CLK_P | A28 | - | D | |||
J1.67 | LVDS1_D1_N | CPU.LVDS1_D1_N | B27 | - | D | |||
J1.69 | LVDS1_D1_P | CPU.LVDS1_D1_P | A27 | - | D | |||
J1.71 | LVDS1_D0_N | CPU.LVDS1_D0_N | B26 | - | D | |||
J1.73 | LVDS1_D0_P | CPU.LVDS1_D0_P | A26 | - | D | |||
J1.75 | DGND | DGND | - | - | G | |||
J1.77 | MIPI_CSI2_D0_P | CPU.MIPI_CSI2_D0_P | A25 | - | D | |||
J1.79 | MIPI_CSI2_D0_N | CPU.MIPI_CSI2_D0_N | B25 | - | D | |||
J1.81 | MIPI_CSI2_D1_P | CPU.MIPI_CSI2_D1_P | A24 | - | D | |||
J1.83 | MIPI_CSI2_D1_N | CPU.MIPI_CSI2_D1_N | B24 | - | D | |||
J1.85 | MIPI_CSI2_CLK_P | CPU.MIPI_CSI2_CLK_P | A23 | - | D | |||
J1.87 | MIPI_CSI2_CLK_N | CPU.MIPI_CSI2_CLK_N | B23 | - | D | |||
J1.89 | MIPI_CSI2_D2_P | CPU.MIPI_CSI2_D2_P | A22 | - | D | |||
J1.91 | MIPI_CSI2_D2_N | CPU.MIPI_CSI2_D2_N | B22 | - | D | |||
J1.93 | MIPI_CSI2_D3_P | CPU.MIPI_CSI2_D3_P | A21 | - | D | |||
J1.95 | MIPI_CSI2_D3_N | CPU.MIPI_CSI2_D3_N | B21 | - | D | |||
J1.97 | DGND | DGND | - | - | G | |||
J1.99 | MIPI_CSI1_D3_P | CPU.MIPI_CSI1_D3_P | D26 | - | D | |||
J1.101 | MIPI_CSI1_D3_N | CPU.MIPI_CSI1_D3_N | E26 | - | D | |||
J1.103 | MIPI_CSI1_D2_P | CPU.MIPI_CSI1_D2_P | D24 | - | D | |||
J1.105 | MIPI_CSI1_D2_N | CPU.MIPI_CSI1_D2_N | E24 | - | D | |||
J1.107 | MIPI_CSI1_CLK_P | CPU.MIPI_CSI1_CLK_P | D22 | - | D | |||
J1.109 | MIPI_CSI1_CLK_N | CPU.MIPI_CSI1_CLK_N | E22 | - | D | |||
J1.111 | MIPI_CSI1_D1_P | CPU.MIPI_CSI1_D1_P | D20 | - | D | |||
J1.113 | MIPI_CSI1_D1_N | CPU.MIPI_CSI1_D1_N | E20 | - | D | |||
J1.115 | MIPI_CSI1_D0_P | CPU.MIPI_CSI1_D0_P | D18 | - | D | |||
J1.117 | MIPI_CSI1_D0_N | CPU.MIPI_CSI1_D0_N | E18 | - | D | |||
J1.119 | DGND | DGND | - | - | G | |||
J1.121 | MIPI_DSI1_D3_P | CPU.MIPI_DSI1_D3_P | A20 | - | D | |||
J1.123 | MIPI_DSI1_D3_N | CPU.MIPI_DSI1_D3_N | B20 | - | D | |||
J1.125 | MIPI_DSI1_D2_P | CPU.MIPI_DSI1_D2_P | A19 | - | D | |||
J1.127 | MIPI_DSI1_D2_N | CPU.MIPI_DSI1_D2_N | B19 | - | D | |||
J1.129 | MIPI_DSI1_CLK_P | CPU.MIPI_DSI1_CLK_P | A18 | - | D | |||
J1.131 | MIPI_DSI1_CLK_N | CPU.MIPI_DSI1_CLK_N | B18 | - | D | |||
J1.133 | MIPI_DSI1_D1_P | CPU.MIPI_DSI1_D1_P | A17 | - | D | |||
J1.135 | MIPI_DSI1_D1_N | CPU.MIPI_DSI1_D1_N | B17 | - | D | |||
J1.137 | MIPI_DSI1_D0_P | CPU.MIPI_DSI1_D0_P | A16 | - | D | |||
J1.139 | MIPI_DSI1_D0_N | CPU.MIPI_DSI1_D0_N | B16 | - | D | |||
J1.141 | DGND | DGND | - | - | G | |||
J1.143 | JTAG_MOD | CPU.JTAG_MOD | G20 | NVCC_3V3 | I/O | |||
J1.145 | JTAG_TCK | CPU.JTAG_TCK | G18 | NVCC_3V3 | I/O | |||
J1.147 | JTAG_TDI | CPU.JTAG_TDI | G16 | NVCC_3V3 | I | |||
J1.149 | JTAG_TMS | CPU.JTAG_TMS | G14 | NVCC_3V3 | I/O | |||
J1.151 | JTAG_TDO | CPU.JTAG_TDO | F14 | NVCC_3V3 | O | |||
J1.153 | DGND | DGND | - | - | G | |||
J1.155 | PCIE_REF_PAD_CLK_P | CPU.PCIE_REF_PAD_CLK_P | D16 | - | D | |||
J1.157 | PCIE_REF_PAD_CLK_N | CPU.PCIE_REF_PAD_CLK_N | E16 | - | D | |||
J1.159 | PCIE_TXN_P | CPU.PCIE_TXN_P | A15 | - | D | |||
J1.161 | PCIE_TXN_N | CPU.PCIE_TXN_N | B15 | - | D | |||
J1.163 | PCIE_RXN_P | CPU.PCIE_RXN_P | A14 | - | D | |||
J1.165 | PCIE_RXN_N | CPU.PCIE_RXN_N | B14 | - | D | |||
J1.167 | DGND | DGND | - | - | G | |||
J1.169 | USB2_VBUS | USB2_VBUS | - | - | S | See USB section for details (5-20V tolerance) | ||
J1.171 | DNU | DNU | - | - | - | DNU stands for Do Not Use.
This pin must be left unconnected/floating. |
||
J1.173 | USB2_D_P | CPU.USB2_D_P | D14 | - | D | |||
J1.175 | USB2_D_N | CPU.USB2_D_N | E14 | - | D | |||
J1.177 | DGND | DGND | - | - | G | |||
J1.179 | USB2_TX_P | CPU.USB2_TX_P | A13 | - | D | |||
J1.181 | USB2_TX_N | CPU.USB2_TX_N | B13 | - | D | |||
J1.183 | USB2_RX_P | CPU.USB2_RX_P | A12 | - | D | |||
J1.185 | USB2_RX_N | CPU.USB2_RX_N | B12 | - | D | |||
J1.187 | DGND | DGND | - | - | G | |||
J1.189 | USB1_VBUS | USB1_VBUS | - | - | S | See USB section for details (5-20V tolerance) | ||
J1.191 | ETH0_INTn | LAN.INT_N/PME_N2 | 38 | VDD_1V8 | O | Must be level translated if used @ 3V3
Internally pulled-up to 1.8V |
||
J1.193 | USB1_D_P | CPU.USB1_D_P | D10 | - | D | |||
J1.195 | USB1_D_N | CPU.USB1_D_N | E10 | - | D | |||
J1.197 | DGND | DGND | - | - | G | |||
J1.199 | USB1_TX_P | CPU.USB1_TX_P | A10 | - | D | |||
J1.201 | USB1_TX_N | CPU.USB1_TX_N | B10 | - | D | |||
J1.203 | USB1_RX_P | CPU.USB1_RX_P | A9 | - | D | |||
J1.205 | USB1_RX_N | CPU.USB1_RX_N | B9 | - | D | |||
J1.207 | DGND | DGND | - | - | G | |||
J1.209 | GPIO1_IO08 | CPU.GPIO1_IO08 | A8 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO08 | |
Pin ALT-1 | ENET_QOS_1588_EVENT0_IN | |||||||
Pin ALT-2 | PWM1_OUT | |||||||
Pin ALT-3 | ISP_PRELIGHT_TRIG_1 | |||||||
Pin ALT-4 | ENET_QOS_1588_EVENT0_AUX_IN | |||||||
Pin ALT-5 | USDHC2_RESET_B | |||||||
J1.211 | GPIO1_IO11 | CPU.GPIO1_IO11 | D8 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO11 | |
Pin ALT-1 | USB2_OTG_ID | |||||||
Pin ALT-2 | PWM2_OUT | |||||||
Pin ALT-4 | USDHC3_VSELECT | |||||||
Pin ALT-5 | CCM_PMIC_READY | |||||||
J1.213 | GPIO1_IO09 | CPU.GPIO1_IO09 | B8 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO09 | |
Pin ALT-1 | ENET_QOS_1588_EVENT0_OUT | |||||||
Pin ALT-2 | PWM2_OUT | |||||||
Pin ALT-3 | ISP_SHUTTER_OPEN_1 | |||||||
Pin ALT-4 | USDHC3_RESET_B | |||||||
Pin ALT-5 | SDMA2_EXT_EVENT00 | |||||||
J1.215 | GPIO1_IO00 | CPU.GPIO1_IO00 | A7 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO00 | |
Pin ALT-1 | CCM_ENET_PHY_REF_CLK_ROOT | |||||||
Pin ALT-3 | ISP_FL_TRIG_0 | |||||||
Pin ALT-6 | CCM_EXT_CLK1 | |||||||
J1.217 | GPIO1_IO01 | CPU.GPIO1_IO01 | E8 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO01 | |
Pin ALT-1 | PWM1_OUT | |||||||
Pin ALT-3 | ISP_SHUTTER_TRIG_0 | |||||||
Pin ALT-6 | CCM_EXT_CLK2 | |||||||
J1.219 | GPIO1_IO10 | CPU.GPIO1_IO10 | B7 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO10 | |
Pin ALT-1 | USB1_OTG_ID | |||||||
Pin ALT-2 | PWM3_OUT | |||||||
J1.221 | GPIO1_IO13 | CPU.GPIO1_IO13 | A6 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO13 | |
Pin ALT-1 | TUSB1_OTG_OCBD | |||||||
Pin ALT-5 | PWM2_OUT | |||||||
J1.223 | GPIO1_IO12 | CPU.GPIO1_IO12 | A5 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO12 | |
Pin ALT-1 | USB1_OTG_PWR | |||||||
Pin ALT-5 | SDMA2_EXT_EVENT01 | |||||||
J1.225 | GPIO1_IO07 | CPU.GPIO1_IO07 | F6 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO07 | |
Pin ALT-1 | ENET_QOS_MDIO | |||||||
Pin ALT-3 | ISP_FLASH_TRIG_1 | |||||||
Pin ALT-5 | USDHC1_WP | |||||||
Pin ALT-6 | CCM_EXT_CLK4 | |||||||
J1.227 | GPIO1_IO15 | CPU.GPIO1_IO15 | B5 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO15 | |
Pin ALT-1 | USB2_OTG_OC | |||||||
Pin ALT-4 | USDHC3_WP | |||||||
Pin ALT-5 | PWM4_OUT | |||||||
Pin ALT-6 | CCM_CLKO2 | |||||||
J1.229 | GPIO1_IO14 | CPU.GPIO1_IO14 | A4 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO14 | |
Pin ALT-1 | USB2_OTG_PWR | |||||||
Pin ALT-4 | USDHC3_CD_B | |||||||
Pin ALT-5 | PWM3_OUT | |||||||
Pin ALT-6 | CCM_CLKO1 | |||||||
J1.231 | GPIO1_IO05 | CPU.GPIO1_IO05 | B4 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO05 | |
Pin ALT-1 | M7_NMI | |||||||
Pin ALT-3 | ISP_FL_TRIG_1 | |||||||
Pin ALT-6 | CCM_PMIC_READY | |||||||
J1.233 | GPIO1_IO06 | CPU.GPIO1_IO06 | A3 | NVCC_3V3 | I/O | Pin ALT-0 | GPIO1_IO06 | |
Pin ALT-1 | ENET_QOS_MDC | |||||||
Pin ALT-3 | ISP_SHUTTER_TRIG_1 | |||||||
Pin ALT-5 | USDHC1_CD_B | |||||||
Pin ALT-6 | CCM_EXT_CLK3 | |||||||
J1.235 | DGND | DGND | - | - | G | |||
J1.237 | ETH0_TXRX3_M | LAN.TXTRM_D | 11 | - | D | |||
J1.239 | ETH0_TXRX3_P | LAN.TXTRP_D | 10 | - | D | |||
J1.241 | ETH0_TXRX2_M | LAN.TXTRM_C | 8 | - | D | |||
J1.243 | ETH0_TXRX2_P | LAN.TXTRP_C | 7 | - | D | |||
J1.245 | ETH0_TXRX1_M | LAN.TXTRM_B | 6 | - | D | |||
J1.247 | ETH0_TXRX1_P | LAN.TXTRP_B | 5 | - | D | |||
J1.249 | ETH0_TXRX0_M | LAN.TXTRM_A | 3 | - | D | |||
J1.251 | ETH0_TXRX0_P | LAN.TXTRP_A | 2 | - | D | |||
J1.253 | DGND | DGND | - | - | G | |||
J1.255 | ETH0_LED1 | LAN.LED2 | 15 | VDD_1V8 | O | Must be level translated if used @ 3V3
Internally pulled-up to 1.8V during bootstrap |
||
J1.257 | ETH0_LED2 | LAN.LED1/PME_N1 | 17 | VDD_1V8 | O | Must be level translated if used @ 3V3
Internally pulled-up to 1.8V during bootstrap |
||
J1.259 | DGND | DGND | - | - | G |
Pinout Table EVEN pins declarationEdit
Pin | Pin Name | Internal Connections | Ball/pin # | Voltage domain | Type | Notes | Alternative Functions | |
---|---|---|---|---|---|---|---|---|
J1.2 | DGND | DGND | - | - | G | |||
J1.4 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.6 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.8 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.10 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.12 | VIN_SOM | INPUT VOLTAGE | - | 3.3VIN | S | |||
J1.14 | DGND | DGND | - | - | G | |||
J1.16 | SD1_CLK | CPU.SD1_CLK | W28 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_CLK | |
Pin ALT-1 | ENET1_MDC | |||||||
Pin ALT-3 | I2C5_SCL | |||||||
Pin ALT-4 | UART1_TX | |||||||
Pin ALT-5 | GPIO2_IO[0] | |||||||
J1.18 | SD1_CMD | CPU.SD1_CMD | W29 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_CMD | |
Pin ALT-1 | ENET1_MDIO | |||||||
Pin ALT-3 | I2C5_SDA | |||||||
Pin ALT-4 | UART1_RX | |||||||
Pin ALT-5 | GPIO2_IO[1] | |||||||
J1.20 | SD1_DATA0 | CPU.SD1_DATA0 | Y29 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_DATA0 | |
Pin ALT-1 | ENET1_RGMII_TD1 | |||||||
Pin ALT-3 | I2C6_SCL | |||||||
Pin ALT-4 | UART1_RTS_B | |||||||
Pin ALT-5 | GPIO2_IO[2] | |||||||
J1.22 | SD1_DATA1 | CPU.SD1_DATA1 | Y28 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_DATA1 | |
Pin ALT-1 | ENET1_RGMII_TD0 | |||||||
Pin ALT-3 | I2C6_SDA | |||||||
Pin ALT-4 | UART1_CTS_B | |||||||
Pin ALT-5 | GPIO2_IO[3] | |||||||
J1.24 | SD1_DATA2 | CPU.SD1_DATA2 | V29 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_DATA2 | |
Pin ALT-1 | ENET1_RGMII_RD0 | |||||||
Pin ALT-3 | I2C4_SCL | |||||||
Pin ALT-4 | UART2_TX | |||||||
Pin ALT-5 | GPIO2_IO[4] | |||||||
J1.26 | SD1_DATA3 | CPU.SD1_DATA3 | V28 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_DATA3 | |
Pin ALT-1 | ENET1_RGMII_RD1 | |||||||
Pin ALT-3 | I2C4_SDA | |||||||
Pin ALT-4 | UART2_RX | |||||||
Pin ALT-5 | GPIO2_IO[5] | |||||||
J1.28 | SD1_DATA4 | CPU.SD1_DATA4 | U26 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_DATA4 | |
Pin ALT-1 | ENET1_RGMII_TX_CTL | |||||||
Pin ALT-3 | I2C1_SCL | |||||||
Pin ALT-4 | UART2_RTS_B | |||||||
Pin ALT-5 | GPIO2_IO[6] | |||||||
J1.30 | SD1_DATA5 | CPU.SD1_DATA5 | AA29 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_DATA5 | |
Pin ALT-1 | ENET1_TX_ER | |||||||
Pin ALT-3 | I2C1_SDA | |||||||
Pin ALT-4 | UART2_CTS_B | |||||||
Pin ALT-5 | GPIO2_IO[7] | |||||||
J1.32 | SD1_DATA6 | CPU.SD1_DATA6 | AA28 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_DATA6 | |
Pin ALT-1 | FLEXSPI_B_DATA[2] | |||||||
Pin ALT-2 | USDHC3_DATA2 | |||||||
Pin ALT-3 | FLEXSPI_A_DATA[6] | |||||||
Pin ALT-4 | ISP_PRELIGHT_TRIG_1 | |||||||
Pin ALT-5 | GPIO3_IO[12] | |||||||
J1.34 | SD1_DATA7 | CPU.SD1_DATA7 | U25 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_DATA7 | |
Pin ALT-1 | ENET1_RX_ER | |||||||
Pin ALT-3 | I2C2_SDA | |||||||
Pin ALT-4 | UART3_RX | |||||||
Pin ALT-5 | GPIO2_IO[9] | |||||||
J1.36 | SD1_RESET_B | CPU.SD1_RESET_B | W25 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_RESET_B | |
Pin ALT-1 | ENET1_TX_CLK | |||||||
Pin ALT-3 | I2C3_SCL | |||||||
Pin ALT-4 | UART3_RTS_B | |||||||
Pin ALT-5 | GPIO2_IO[10] | |||||||
J1.38 | SD1_STROBE | CPU.SD1_STROBE | W26 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC1_STROBE | |
Pin ALT-3 | I2C3_SDA | |||||||
Pin ALT-4 | UART3_CTS_B | |||||||
Pin ALT-5 | GPIO2_IO[11] | |||||||
J1.40 | DGND | DGND | - | - | G | |||
J1.42 | SD2_CD_B | CPU.SD2_CD_B | AD29 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC2_CD_B | |
Pin ALT-5 | GPIO2_IO[12] | |||||||
J1.44 | SD2_CLK | CPU.SD2_CLK | AB29 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC2_CLK | |
Pin ALT-2 | ECSPI2_SCLK | |||||||
Pin ALT-3 | UART4_RX | |||||||
Pin ALT-5 | GPIO2_IO[13] | |||||||
J1.46 | SD2_CMD | CPU.SD2_CMD | AB28 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC2_CMD | |
Pin ALT-2 | ECSPI2_MOSI | |||||||
Pin ALT-3 | UART4_TX | |||||||
Pin ALT-4 | AUDIOMIX_CLK | |||||||
Pin ALT-5 | GPIO2_IO[14] | |||||||
J1.48 | SD2_DATA0 | CPU.SD2_DATA0 | AC28 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC2_DATA0 | |
Pin ALT-2 | I2C4_SDA | |||||||
Pin ALT-3 | UART2_RX | |||||||
Pin ALT-4 | AUDIOMIX_BIT_STREAM[0] | |||||||
Pin ALT-5 | GPIO2_IO[15] | |||||||
J1.50 | SD2_DATA1 | CPU.SD2_DATA1 | AC29 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC2_DATA1 | |
Pin ALT-2 | I2C4_SCL | |||||||
Pin ALT-3 | UART2_TX | |||||||
Pin ALT-4 | AUDIOMIX_BIT_STREAM[1] | |||||||
Pin ALT-5 | GPIO2_IO[16] | |||||||
J1.52 | SD2_DATA2 | CPU.SD2_DATA2 | AA26 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC2_DATA2 | |
Pin ALT-2 | ECSPI2_SS0 | |||||||
Pin ALT-3 | AUDIOMIX_SPDIF_OUT | |||||||
Pin ALT-4 | AUDIOMIX_BIT_STREAM[2] | |||||||
Pin ALT-5 | GPIO2_IO[17] | |||||||
J1.54 | SD2_DATA3 | CPU.SD2_DATA3 | AA25 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC2_DATA3 | |
Pin ALT-2 | ECSPI2_MISO | |||||||
Pin ALT-3 | AUDIOMIX_SPDIF_IN | |||||||
Pin ALT-4 | AUDIOMIX_BIT_STREAM[3] | |||||||
Pin ALT-5 | GPIO2_IO[18] | |||||||
Pin ALT-6 | SRC_EARLY_RESET | |||||||
J1.56 | SD2_RESET_B | CPU.SD2_RESET_B | AD28 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC2_RESET_B | |
Pin ALT-5 | GPIO2_IO[19] | |||||||
Pin ALT-6 | SRC_SYSTEM_RESET | |||||||
J1.58 | SD2_WP | CPU.SD2_WP | AC26 | NVCC_3V3 | I/O | Pin ALT-0 | USDHC2_WP | |
Pin ALT-5 | GPIO2_IO[20] | |||||||
Pin ALT-6 | CORESIGHT_EVENTI | |||||||
J1.58
(both NAND and NOR on board) |
SD2_WP | CPU.SD2_WP | AC26 | NVCC_3V3 | O | internal use for
NAND/NOR selection, do not connect |
||
J1.60 | DGND | DGND | - | - | G | |||
J1.62 | CLKIN1 | CPU.CLKIN1 | K28 | NVCC_3V3 | I | |||
J1.64 | CLKIN2 | CPU.CLKIN2 | L28 | NVCC_3V3 | I | |||
J1.66 | DGND | DGND | - | - | G | |||
J1.68 | CLKOUT1 | CPU.CLKOUT1 | K29 | NVCC_3V3 | O | |||
J1.70 | CLKOUT2 | CPU.CLKOUT2 | L29 | NVCC_3V3 | O | |||
J1.72 | DGND | DGND | - | - | G | |||
J1.74 | HDMI_CEC | CPU.HDMI_CEC | AD22 | NVCC_3V3 | I/O | Pin ALT-0 | HDMIMIX_EARC_CEC | |
Pin ALT-3 | I2C6_SCL | |||||||
Pin ALT-4 | CAN2_TX | |||||||
Pin ALT-5 | GPIO3_IO[28] | |||||||
J1.76 | HDMI_DDC_SCL | CPU.HDMI_DDC_SCL | AC22 | NVCC_3V3 | I/O | Pin ALT-0 | HDMIMIX_EARC_SCL | |
Pin ALT-3 | I2C5_SCL | |||||||
Pin ALT-4 | CAN1_TX | |||||||
Pin ALT-5 | GPIO3_IO[26] | |||||||
J1.78 | HDMI_DDC_SDA | CPU.HDMI_DDC_SDA | AF22 | NVCC_3V3 | I/O | Pin ALT-0 | HDMIMIX_EARC_SDA | |
Pin ALT-3 | I2C5_SDA | |||||||
Pin ALT-4 | CAN1_RX | |||||||
Pin ALT-5 | GPIO3_IO[27] | |||||||
J1.80 | HDMI_HPD | CPU.HDMI_HPD | AE22 | NVCC_3V3 | I/O | Pin ALT-0 | HDMIMIX_EARC_DC_HPD | |
Pin ALT-1 | AUDIOMIX_EARC_HDMI_HPD_O | |||||||
Pin ALT-3 | I2C6_SDA | |||||||
Pin ALT-4 | CAN2_RX | |||||||
Pin ALT-5 | GPIO3_IO[29] | |||||||
J1.82 | DGND | DGND | - | - | G | |||
J1.84 | HDMI_TXC_N | CPU.HDMI_TXC_N | AJ24 | - | D | |||
J1.86 | HDMI_TXC_P | CPU.HDMI_TXC_P | AH24 | - | D | |||
J1.88 | HDMI_TX0_N | CPU.HDMI_TX0_N | AJ25 | - | D | |||
J1.90 | HDMI_TX0_P | CPU.HDMI_TX0_P | AH25 | - | D | |||
J1.92 | HDMI_TX1_N | CPU.HDMI_TX1_N | AJ26 | - | D | |||
J1.94 | HDMI_TX1_P | CPU.HDMI_TX1_P | AH26 | - | D | |||
J1.96 | HDMI_TX2_N | CPU.HDMI_TX2_N | AJ27 | - | D | |||
J1.98 | HDMI_TX2_P | CPU.HDMI_TX2_P | AH27 | - | D | |||
J1.100 | DGND | DGND | - | - | G | |||
J1.102 | EARC_P_UTIL | CPU.EARC_P_UTIL | AJ23 | VDDA_1V8 | D | |||
J1.104 | EARC_N_HPD | CPU.EARC_N_HPD | AH22 | VDDA_1V8 | D | |||
J1.106 | EARC_AUX | CPU.EARC_AUX | AH23 | VDDA_1V8 | I/O | |||
J1.108 | DGND | DGND | - | - | G | |||
J1.110 | ECSPI1_MISO | CPU.ECSPI1_MISO | AD20 | NVCC_3V3 | I/O | Pin ALT-0 | ECSPI1_MISO | |
Pin ALT-1 | UART3_CTS_B | |||||||
Pin ALT-2 | I2C2_SCL | |||||||
Pin ALT-3 | AUDIOMIX_SAI7_RX_DATA[0] | |||||||
Pin ALT-5 | GPIO5_IO[8] | |||||||
J1.112 | ECSPI1_MOSI | CPU.ECSPI1_MOSI | AC20 | NVCC_3V3 | I/O | Pin ALT-0 | ECSPI1_MOSI | |
Pin ALT-1 | UART3_TX | |||||||
Pin ALT-2 | I2C1_SDA | |||||||
Pin ALT-3 | AUDIOMIX_SAI7_RX_BCLK | |||||||
Pin ALT-5 | GPIO5_IO[7] | |||||||
J1.114 | ECSPI1_SCLK | CPU.ECSPI1_SCLK | AF20 | NVCC_3V3 | I/O | Pin ALT-0 | ECSPI1_SCLK | |
Pin ALT-1 | UART3_RX | |||||||
Pin ALT-2 | I2C1_SCL | |||||||
Pin ALT-3 | AUDIOMIX_SAI7_RX_SYNC | |||||||
Pin ALT-5 | GPIO5_IO[6] | |||||||
J1.116 | ECSPI1_SS0 | CPU.ECSPI1_SS0 | AE20 | NVCC_3V3 | I/O | Pin ALT-0 | ECSPI1_SS0 | |
Pin ALT-1 | UART3_RTS_B | |||||||
Pin ALT-2 | I2C2_SDA | |||||||
Pin ALT-3 | AUDIOMIX_SAI7_TX_SYNC | |||||||
Pin ALT-5 | GPIO5_IO[9] | |||||||
J1.118 | DGND | DGND | - | - | G | |||
J1.120 | ECSPI2_MISO | CPU.ECSPI2_MISO | AH20 | NVCC_3V3 | I/O | Pin ALT-0 | ECSPI2_MISO | |
Pin ALT-1 | UART4_CTS_B | |||||||
Pin ALT-2 | I2C4_SCL | |||||||
Pin ALT-3 | AUDIOMIX_SAI7_MCLK | |||||||
Pin ALT-4 | CCM_CLKO1 | |||||||
Pin ALT-5 | GPIO5_IO[12] | |||||||
J1.122 | ECSPI2_MOSI | CPU.ECSPI2_MOSI | AJ21 | NVCC_3V3 | I/O | Pin ALT-0 | ECSPI2_MOSI | |
Pin ALT-1 | UART4_TX | |||||||
Pin ALT-2 | I2C3_SDA | |||||||
Pin ALT-3 | AUDIOMIX_SAI7_TX_DATA[0] | |||||||
Pin ALT-5 | GPIO5_IO[11] | |||||||
J1.124 | ECSPI2_SCLK | CPU.ECSPI2_SCLK | AH21 | NVCC_3V3 | I/O | Pin ALT-0 | ECSPI2_SCLK | |
Pin ALT-1 | UART4_RX | |||||||
Pin ALT-2 | I2C3_SCL | |||||||
Pin ALT-3 | AUDIOMIX_SAI7_TX_BCLK | |||||||
Pin ALT-5 | GPIO5_IO[10] | |||||||
J1.126 | ECSPI2_SS0 | CPU.ECSPI2_SS0 | AJ22 | NVCC_3V3 | I/O | Pin ALT-0 | ECSPI2_SS0 | |
Pin ALT-1 | UART4_RTS_B | |||||||
Pin ALT-2 | I2C4_SDA | |||||||
Pin ALT-4 | CCM_CLKO2 | |||||||
Pin ALT-5 | GPIO5_IO[13] | |||||||
J1.128 | DGND | DGND | - | - | G | |||
J1.130 | SPDIF_EXT_CLK//
ISP_FL_TRIG_0 |
CPU.SPDIF_EXT_CLK | AC18 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SPDIF or ISP (*) |
Pin ALT-0 | AUDIOMIX_SPDIF_EXT_CLK |
Pin ALT-1 | PWM1_OUT | |||||||
Pin ALT-3 | GPT1_COMPARE3 | |||||||
Pin ALT-5 | GPIO5_IO[5] | |||||||
J1.132 | SPDIF_RX//
ISP_SHUTTER_TRIG_0 |
CPU.SPDIF_RX | AD18 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SPDIF or ISP (*) |
Pin ALT-0 | AUDIOMIX_SPDIF_IN |
Pin ALT-1 | PWM2_OUT | |||||||
Pin ALT-2 | I2C5_SDA | |||||||
Pin ALT-3 | GPT1_COMPARE2 | |||||||
Pin ALT-4 | CAN1_RX | |||||||
Pin ALT-5 | GPIO5_IO[4] | |||||||
J1.134 | SPDIF_TX//
ISP_FLASH_TRIG_0 |
CPU.SPDIF_TX | AE18 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SPDIF or ISP (*) |
Pin ALT-0 | AUDIOMIX_SPDIF_OUT |
Pin ALT-1 | PWM3_OUT | |||||||
Pin ALT-2 | I2C5_SCL | |||||||
Pin ALT-3 | GPT1_COMPARE1 | |||||||
Pin ALT-4 | CAN1_TX | |||||||
Pin ALT-5 | GPIO5_IO[3] | |||||||
J1.136 | DGND | DGND | - | - | G | |||
J1.138 | SAI2_MCLK | CPU.SAI2_MCLK | AJ15 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI2_MCLK | |
Pin ALT-1 | AUDIOMIX_SAI5_MCLK | |||||||
Pin ALT-2 | ENET_QOS_1588_EVENT3_IN | |||||||
Pin ALT-3 | CAN2_RX | |||||||
Pin ALT-4 | ENET_QOS_1588_EVENT3_AUX_IN | |||||||
Pin ALT-5 | GPIO4_IO[27] | |||||||
Pin ALT-6 | AUDIOMIX_SAI3_MCLK | |||||||
J1.140 | SAI2_RXC | CPU.SAI2_RXC | AJ16 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI2_RX_BCLK | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_BCLK | |||||||
Pin ALT-3 | CAN1_TX | |||||||
Pin ALT-4 | UART1_RX | |||||||
Pin ALT-5 | GPIO4_IO[22] | |||||||
Pin ALT-6 | AUDIOMIX_BIT_STREAM[1] | |||||||
J1.142 | SAI2_RXD0 | CPU.SAI2_RXD0 | AJ14 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI2_RX_DATA[0] | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_DATA[0] | |||||||
Pin ALT-2 | ENET_QOS_1588_EVENT2_OUT | |||||||
Pin ALT-3 | AUDIOMIX_SAI2_TX_DATA[1] | |||||||
Pin ALT-4 | UART1_RTS_B | |||||||
Pin ALT-5 | GPIO4_IO[23] | |||||||
Pin ALT-6 | AUDIOMIX_PDM_BIT_STREAM[3] | |||||||
J1.144 | SAI2_RXFS | CPU.SAI2_RXFS | AH17 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI2_RX_SYNC | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_SYNC | |||||||
Pin ALT-2 | AUDIOMIX_SAI5_TX_DATA[1] | |||||||
Pin ALT-3 | AUDIOMIX_SAI2_RX_DATA[1] | |||||||
Pin ALT-4 | UART1_TX | |||||||
Pin ALT-5 | GPIO4_IO[21] | |||||||
Pin ALT-6 | AUDIOMIX_BIT_STREAM[2] | |||||||
J1.146 | SAI2_TXC | CPU.SAI2_TXC | AH15 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI2_TX_BCLK | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_DATA[2] | |||||||
Pin ALT-3 | CAN1_RX | |||||||
Pin ALT-5 | GPIO4_IO[25] | |||||||
Pin ALT-6 | AUDIOMIX_BIT_STREAM[1] | |||||||
J1.148 | SAI2_TXD0 | CPU.SAI2_TXD0 | AH16 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI2_TX_DATA[0] | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_DATA[3] | |||||||
Pin ALT-2 | ENET_QOS_1588_EVENT2_IN | |||||||
Pin ALT-3 | CAN2_TX | |||||||
Pin ALT-4 | ENET_QOS_1588_EVENT2_AUX_IN | |||||||
Pin ALT-5 | GPIO4_IO[26] | |||||||
J1.150 | SAI2_TXFS | CPU.SAI2_TXFS | AJ17 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI2_TX_SYNC | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_DATA[1] | |||||||
Pin ALT-2 | ENET_QOS_1588_EVENT3_OUT | |||||||
Pin ALT-3 | AUDIOMIX_SAI2_TX_DATA[1] | |||||||
Pin ALT-4 | UART1_CTS_B | |||||||
Pin ALT-5 | GPIO4_IO[24] | |||||||
Pin ALT-6 | AUDIOMIX_PDM_BIT_STREAM[2] | |||||||
J1.152 | SAI3_MCLK//
ISP_PRELIGHT_TRIG_0 |
CPU.SAI3_MCLK | AJ20 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SPDIF or ISP (*) |
Pin ALT-0 | AUDIOMIX_SAI3_MCLK |
Pin ALT-1 | PWM4_OUT | |||||||
Pin ALT-2 | AUDIOMIX_SAI5_MCLK | |||||||
Pin ALT-4 | AUDIOMIX_SPDIF_OUT | |||||||
Pin ALT-5 | GPIO5_IO[2] | |||||||
Pin ALT-6 | AUDIOMIX_SPDIF_IN | |||||||
J1.154 | SAI3_RXC//
ISP_SHUTTER_OPEN_0 |
CPU.SAI3_RXC | AJ18 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SPDIF or ISP (*) |
Pin ALT-0 | AUDIOMIX_SAI3_RX_BCLK |
Pin ALT-1 | AUDIOMIX_SAI2_RX_DATA[2] | |||||||
Pin ALT-2 | AUDIOMIX_SAI5_RX_BCLK | |||||||
Pin ALT-3 | GPT1_CLK | |||||||
Pin ALT-4 | UART2_CTS_B | |||||||
Pin ALT-5 | GPIO4_IO[29] | |||||||
Pin ALT-6 | AUDIOMIX_CLK | |||||||
J1.156 | SAI3_RXD//
ISP_FL_TRIG_1 |
CPU.SAI3_RXD | AF18 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SPDIF or ISP (*) |
Pin ALT-0 | AUDIOMIX_SAI3_RX_DATA[0] |
Pin ALT-1 | AUDIOMIX_SAI2_RX_DATA[3] | |||||||
Pin ALT-2 | AUDIOMIX_SAI5_RX_DATA[0] | |||||||
Pin ALT-4 | UART2_RTS_B | |||||||
Pin ALT-5 | GPIO4_IO[30] | |||||||
Pin ALT-6 | AUDIOMIX_BIT_STREAM[1] | |||||||
J1.158 | SAI3_RXFS//
ISP_SHUTTER_TRIG_1 |
CPU.SAI3_RXFS | AJ19 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SPDIF or ISP (*) |
Pin ALT-0 | AUDIOMIX_SAI3_RX_SYNC |
Pin ALT-1 | AUDIOMIX_SAI2_RX_DATA[1] | |||||||
Pin ALT-2 | AUDIOMIX_SAI5_RX_SYNC | |||||||
Pin ALT-3 | AUDIOMIX_SAI3_RX_DATA[1] | |||||||
Pin ALT-4 | AUDIOMIX_SPDIF1_IN | |||||||
Pin ALT-5 | GPIO4_IO[28] | |||||||
Pin ALT-6 | AUDIOMIX_PDM_BIT_STREAM[0] | |||||||
J1.160 | SAI3_TXC//
ISP_FLASH_TRIG_1 |
CPU.SAI3_TXC | AH19 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SPDIF or ISP (*) |
Pin ALT-0 | AUDIOMIX_SAI3_TX_BCLK |
Pin ALT-1 | AUDIOMIX_SAI2_TX_DATA[2] | |||||||
Pin ALT-2 | AUDIOMIX_SAI5_RX_DATA[2] | |||||||
Pin ALT-3 | GPT1_CAPTURE1 | |||||||
Pin ALT-4 | UART2_TX | |||||||
Pin ALT-5 | GPIO5_IO[0] | |||||||
Pin ALT-6 | AUDIOMIX_PDM_BIT_STREAM[2] | |||||||
J1.162 | SAI3_TXD//
ISP_PRELIGHT_TRIG_1 |
CPU.SAI3_TXD | AH18 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SPDIF or ISP (*) |
Pin ALT-0 | AUDIOMIX_SAI3_TX_DATA[0] |
Pin ALT-1 | AUDIOMIX_SAI2_TX_DATA[3] | |||||||
Pin ALT-2 | AUDIOMIX_SAI5_RX_DATA[3] | |||||||
Pin ALT-3 | GPT1_CAPTURE2 | |||||||
Pin ALT-4 | AUDIOMIX_SPDIF_EXT_CLK | |||||||
Pin ALT-5 | GPIO5_IO[1] | |||||||
Pin ALT-6 | SRC_BOOT_MODE[5] | |||||||
J1.164 | SAI3_TXFS//
ISP_SHUTTER_OPEN_1 |
CPU.SAI3_TXFS | AC16 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SPDIF or ISP (*) |
Pin ALT-0 | AUDIOMIX_SAI3_TX_SYNC |
Pin ALT-1 | AUDIOMIX_SAI2_TX_DATA[1] | |||||||
Pin ALT-2 | AUDIOMIX_SAI5_RX_DATA[1] | |||||||
Pin ALT-3 | AUDIOMIX_SAI3_TX_DATA[1] | |||||||
Pin ALT-4 | UART2_RX | |||||||
Pin ALT-5 | GPIO4_IO[31] | |||||||
Pin ALT-6 | AUDIOMIX_PDM_BIT_STREAM[3] | |||||||
J1.166 | SAI5_MCLK | CPU.SAI5_MCLK | AF14 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI5_MCLK | |
Pin ALT-1 | AUDIOMIX_SAI1_TX_BCLK | |||||||
Pin ALT-2 | PWM1_OUT | |||||||
Pin ALT-3 | I2C5_SDA | |||||||
Pin ALT-5 | GPIO3_IO[25] | |||||||
Pin ALT-6 | CAN2_RX | |||||||
J1.168 | SAI5_RXC | CPU.SAI5_RXC | AD14 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI5_RX_BCLK | |
Pin ALT-1 | AUDIOMIX_SAI1_TX_DATA[1] | |||||||
Pin ALT-2 | PWM3_OUT | |||||||
Pin ALT-3 | I2C6_SDA | |||||||
Pin ALT-4 | AUDIOMIX_CLK | |||||||
Pin ALT-5 | GPIO3_IO[20] | |||||||
J1.170 | SAI5_RXD0//
ISO_14443_LA |
CPU.SAI5_RXD0 | AE16 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SAI5 or SE050 ISO (**) |
Pin ALT-0 | AUDIOMIX_SAI5_RX_DATA[0] |
Pin ALT-1 | AUDIOMIX_SAI1_TX_DATA[2] | |||||||
Pin ALT-2 | PWM2_OUT | |||||||
Pin ALT-3 | I2C5_SCL | |||||||
Pin ALT-4 | AUDIOMIX_BIT_STREAM[0] | |||||||
Pin ALT-5 | GPIO3_IO[21] | |||||||
J1.172 | SAI5_RXD1//
ISO_14443_LB |
CPU.SAI5_RXD1 | AD16 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SAI5 or SE050 ISO (**) |
Pin ALT-0 | AUDIOMIX_SAI5_RX_DATA[1] |
Pin ALT-1 | AUDIOMIX_SAI1_TX_DATA[3] | |||||||
Pin ALT-2 | AUDIOMIX_SAI1_TX_SYNC | |||||||
Pin ALT-3 | AUDIOMIX_SAI5_TX_SYNC | |||||||
Pin ALT-4 | AUDIOMIX_BIT_STREAM[1] | |||||||
Pin ALT-5 | GPIO3_IO[22] | |||||||
Pin ALT-6 | CAN1_TX | |||||||
J1.174 | SAI5_RXD2//
ISO_7816_CLK |
CPU.SAI5_RXD2 | AF16 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SAI5 or SE050 ISO (**) |
Pin ALT-0 | AUDIOMIX_SAI5_RX_DATA[2] |
Pin ALT-1 | AUDIOMIX_SAI1_TX_DATA[4] | |||||||
Pin ALT-2 | AUDIOMIX_SAI1_TX_SYNC | |||||||
Pin ALT-3 | AUDIOMIX_SAI5_TX_BCLK | |||||||
Pin ALT-4 | AUDIOMIX_BIT_STREAM[2] | |||||||
Pin ALT-5 | GPIO3_IO[23] | |||||||
Pin ALT-6 | CAN1_RX | |||||||
J1.176 | SAI5_RXD3//
ISO_7816_RST_N |
CPU.SAI5_RXD3 | AE14 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SAI5 or SE050 ISO (**) |
Pin ALT-0 | AUDIOMIX_SAI5_RX_DATA[3] |
Pin ALT-1 | AUDIOMIX_SAI1_TX_DATA[5] | |||||||
Pin ALT-2 | AUDIOMIX_SAI1_TX_SYNC | |||||||
Pin ALT-3 | AUDIOMIX_SAI5_TX_DATA[0] | |||||||
Pin ALT-4 | AUDIOMIX_PDM_BIT_STREAM[3] | |||||||
Pin ALT-5 | GPIO3_IO[24] | |||||||
Pin ALT-6 | CAN2_TX | |||||||
J1.178 | SAI5_RXFS//
SE050_ENA |
CPU.SAI5_RXFS | AC14 | NVCC_3V3 | I/O | Hardware mounting option depending on order code
SAI5 or SE050 (**) |
Pin ALT-0 | AUDIOMIX_SAI5_RX_SYNC |
Pin ALT-1 | AUDIOMIX_SAI1_TX_DATA[0] | |||||||
Pin ALT-2 | PWM4_OUT | |||||||
Pin ALT-3 | I2C6_SCL | |||||||
Pin ALT-5 | GPIO3_IO[19] | |||||||
J1.180 | DGND | DGND | - | - | G | |||
J1.182 | SAI1_MCLK | CPU.SAI1_MCLK | AE12 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_MCLK | |
Pin ALT-1 | AUDIOMIX_SAI1_TX_BCLK | |||||||
Pin ALT-4 | ENET1_TX_CLK | |||||||
Pin ALT-5 | GPIO4_IO[20] | |||||||
J1.184 | SAI1_RXC | CPU.SAI1_RXC | AH8 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_RX_BCLK | |
Pin ALT-1 | AUDIOMIX_PDM_CLK | |||||||
Pin ALT-4 | ENET1_1588_EVENT0_OUT | |||||||
Pin ALT-5 | GPIO4_IO[1] | |||||||
J1.186 | SAI1_RXD0 | CPU.SAI1_RXD0 | AC10 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_RX_DATA[0] | |
Pin ALT-2 | AUDIOMIX_SAI1_TX_DATA[1] | |||||||
Pin ALT-3 | AUDIOMIX_PDM_BIT_STREAM[0] | |||||||
Pin ALT-4 | ENET1_1588_EVENT1_IN | |||||||
Pin ALT-5 | GPIO4_IO[2] | |||||||
J1.188 | SAI1_RXD1 | CPU.SAI1_RXD1 | AF10 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_RX_DATA[1] | |
Pin ALT-3 | AUDIOMIX_PDM_BIT_STREAM[1] | |||||||
Pin ALT-4 | ENET1_1588_EVENT1_OUT | |||||||
Pin ALT-5 | GPIO4_IO[3] | |||||||
J1.190 | SAI1_RXD2 | CPU.SAI1_RXD2 | AH9 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_RX_DATA[2] | |
Pin ALT-1 | AUDIOMIX_SAI5_RX_DATA[2] | |||||||
Pin ALT-3 | AUDIOMIX_BIT_STREAM[2] | |||||||
Pin ALT-4 | ENET1_MDC | |||||||
Pin ALT-5 | GPIO4_IO[4] | |||||||
J1.192 | SAI1_RXD3 | CPU.SAI1_RXD3 | AJ8 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_RX_DATA[3] | |
Pin ALT-1 | AUDIOMIX_SAI5_RX_DATA[3] | |||||||
Pin ALT-3 | AUDIOMIX_BIT_STREAM[3] | |||||||
Pin ALT-4 | ENET1_MDIO | |||||||
Pin ALT-5 | GPIO4_IO[5] | |||||||
J1.194 | SAI1_RXD4 | CPU.SAI1_RXD4 | AD10 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_RX_DATA[4] | |
Pin ALT-1 | AUDIOMIX_SAI6_TX_BCLK | |||||||
Pin ALT-2 | AUDIOMIX_SAI6_RX_BCLK | |||||||
Pin ALT-4 | ENET1_RGMII_RD0 | |||||||
Pin ALT-5 | GPIO4_IO[6] | |||||||
J1.196 | SAI1_RXD5 | CPU.SAI1_RXD5 | AE10 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_RX_DATA[5] | |
Pin ALT-1 | AUDIOMIX_SAI6_TX_DATA[0] | |||||||
Pin ALT-2 | AUDIOMIX_SAI6_RX_DATA[0] | |||||||
Pin ALT-3 | AUDIOMIX_SAI1_RX_SYNC | |||||||
Pin ALT-4 | ENET1_RGMII_RD1 | |||||||
Pin ALT-5 | GPIO4_IO[7] | |||||||
J1.198 | SAI1_RXD6 | CPU.SAI1_RXD6 | AH10 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_RX_DATA[6] | |
Pin ALT-1 | AUDIOMIX_SAI6_TX_SYNC | |||||||
Pin ALT-2 | AUDIOMIX_SAI6_RX_SYNC | |||||||
Pin ALT-4 | ENET1_RGMII_RD2 | |||||||
Pin ALT-5 | GPIO4_IO[8] | |||||||
J1.200 | SAI1_RXD7 | CPU.SAI1_RXD7 | AH12 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_RX_DATA[7] | |
Pin ALT-1 | AUDIOMIX_SAI6_MCLK | |||||||
Pin ALT-2 | AUDIOMIX_SAI1_TX_SYNC | |||||||
Pin ALT-3 | AUDIOMIX_SAI1_TX_DATA[4] | |||||||
Pin ALT-4 | ENET1_RGMII_RD3 | |||||||
Pin ALT-5 | GPIO4_IO[9] | |||||||
J1.202 | SAI1_RXFS | CPU.SAI1_RXFS | AJ9 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_RX_SYNC | |
Pin ALT-4 | ENET1_1588_EVENT0_IN | |||||||
Pin ALT-5 | GPIO4_IO[0] | |||||||
J1.204 | SAI1_TXC | CPU.SAI1_TXC | AJ12 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_TX_BCLK | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_BCLK | |||||||
Pin ALT-4 | ENET1_RGMII_RXC | |||||||
Pin ALT-5 | GPIO4_IO[11] | |||||||
J1.206 | SAI1_TXD0 | CPU.SAI1_TXD0 | AJ11 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_TX_DATA[0] | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_DATA[0] | |||||||
Pin ALT-4 | ENET1_RGMII_TD0 | |||||||
Pin ALT-5 | GPIO4_IO[12] | |||||||
J1.208 | SAI1_TXD1 | CPU.SAI1_TXD1 | AJ10 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_TX_DATA[1] | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_DATA[1] | |||||||
Pin ALT-4 | ENET1_RGMII_TD1 | |||||||
Pin ALT-5 | GPIO4_IO[13] | |||||||
J1.210 | SAI1_TXD2 | CPU.SAI1_TXD2 | AH11 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_TX_DATA[2] | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_DATA[2] | |||||||
Pin ALT-4 | ENET1_RGMII_TD2 | |||||||
Pin ALT-5 | GPIO4_IO[14] | |||||||
J1.212 | SAI1_TXD3 | CPU.SAI1_TXD3 | AD12 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_TX_DATA[3] | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_DATA[3] | |||||||
Pin ALT-4 | ENET1_RGMII_TD3 | |||||||
Pin ALT-5 | GPIO4_IO[15] | |||||||
J1.214 | SAI1_TXD4 | CPU.SAI1_TXD4 | AH13 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_TX_DATA[4] | |
Pin ALT-1 | AUDIOMIX_SAI6_RX_BCLK | |||||||
Pin ALT-2 | AUDIOMIX_SAI6_TX_BCLK | |||||||
Pin ALT-4 | ENET1_RGMII_TX_CTL | |||||||
Pin ALT-5 | GPIO4_IO[16] | |||||||
J1.216 | SAI1_TXD5 | CPU.SAI1_TXD5 | AH14 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_TX_DATA[5] | |
Pin ALT-1 | AUDIOMIX_SAI6_RX_DATA[0] | |||||||
Pin ALT-2 | AUDIOMIX_SAI6_TX_DATA[0] | |||||||
Pin ALT-4 | ENET1_RGMII_TXC | |||||||
Pin ALT-5 | GPIO4_IO[17] | |||||||
J1.218 | SAI1_TXD6 | CPU.SAI1_TXD6 | AC12 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_TX_DATA[6] | |
Pin ALT-1 | AUDIOMIX_SAI6_RX_SYNC | |||||||
Pin ALT-2 | AUDIOMIX_SAI6_TX_SYNC | |||||||
Pin ALT-4 | ENET1_RX_ER | |||||||
Pin ALT-5 | GPIO4_IO[18] | |||||||
J1.220 | SAI1_TXD7 | CPU.SAI1_TXD7 | AJ13 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_TX_DATA[7] | |
Pin ALT-1 | AUDIOMIX_SAI6_MCLK | |||||||
Pin ALT-3 | AUDIOMIX_CLK | |||||||
Pin ALT-4 | ENET1_TX_ER | |||||||
Pin ALT-5 | GPIO4_IO[19] | |||||||
J1.222 | SAI1_TXFS | CPU.SAI1_TXFS | AF12 | NVCC_3V3 | I/O | Pin ALT-0 | AUDIOMIX_SAI1_TX_SYNC | |
Pin ALT-1 | AUDIOMIX_SAI5_TX_SYNC | |||||||
Pin ALT-4 | ENET1_RGMII_RX_CTL | |||||||
Pin ALT-5 | GPIO4_IO[10] | |||||||
J1.224 | DGND | DGND | - | - | G | |||
J1.226
(SE on board) |
I2C1_SCL//
I2C_SCL_SE050 |
SE.ISO 7816 IO2 | 16 | SE_VOUT | I/O | see SE section for
more details |
||
J1.226 | I2C1_SCL//
I2C_SCL_SE050 |
CPU.I2C1_SCL | AC8 | NVCC_3V3 | I/O | Pin ALT-0 | I2C1_SCL | |
Pin ALT-1 | ENET_QOS_MDC | |||||||
Pin ALT-3 | ECSPI1_SCLK | |||||||
Pin ALT-5 | GPIO5_IO[14] | |||||||
J1.228
(SE on board) |
I2C1_SDA//
I2C_SDA_SE050 |
SE.ISO 7816 IO1 | 3 | SE_VOUT | I/O | see SE section for
more details |
||
J1.228 | I2C1_SDA//
I2C_SDA_SE050 |
CPU.I2C1_SDA | AH7 | NVCC_3V3 | I/O | Pin ALT-0 | I2C1_SDA | |
Pin ALT-1 | ENET_QOS_MDIO | |||||||
Pin ALT-3 | ECSPI1_MOSI | |||||||
Pin ALT-5 | GPIO5_IO[15] | |||||||
J1.230 | I2C2_SCL | CPU.I2C2_SCL | AH6 | NVCC_3V3 | I/O | Pin ALT-0 | I2C2_SCL | |
Pin ALT-1 | ENET_QOS_1588_EVENT1_IN | |||||||
Pin ALT-2 | USDHC3_CD_B | |||||||
Pin ALT-3 | ECSPI1_MISO | |||||||
Pin ALT-4 | ENET_QOS_1588_EVENT1_AUX_IN | |||||||
Pin ALT-5 | GPIO5_IO[16] | |||||||
J1.232 | I2C2_SDA | CPU.I2C2_SDA | AE8 | NVCC_3V3 | I/O | Pin ALT-0 | I2C2_SDA | |
Pin ALT-1 | ENET_QOS_1588_EVENT1_OUT | |||||||
Pin ALT-2 | USDHC3_WP | |||||||
Pin ALT-3 | ECSPI1_SS0 | |||||||
Pin ALT-5 | GPIO5_IO[17] | |||||||
J1.234 | I2C3_SCL | CPU.I2C3_SCL | AJ7 | NVCC_3V3 | I/O | Pin ALT-0 | I2C3_SCL | |
Pin ALT-1 | PWM4_OUT | |||||||
Pin ALT-2 | GPT2_CLK | |||||||
Pin ALT-3 | ECSPI2_SCLK | |||||||
Pin ALT-5 | GPIO5_IO[18] | |||||||
J1.236 | I2C3_SDA | CPU.I2C3_SDA | AJ6 | NVCC_3V3 | I/O | Pin ALT-0 | I2C3_SDA | |
Pin ALT-1 | PWM3_OUT | |||||||
Pin ALT-2 | GPT3_CLK | |||||||
Pin ALT-3 | ECSPI2_MOSI | |||||||
Pin ALT-5 | GPIO5_IO[19] | |||||||
J1.238 | I2C4_SCL | CPU.I2C4_SCL | AF8 | NVCC_3V3 | I/O | Pin ALT-0 | I2C4_SCL | |
Pin ALT-1 | PWM2_OUT | |||||||
Pin ALT-2 | PCIE_CLKREQ_B | |||||||
Pin ALT-3 | ECSPI2_MISO | |||||||
Pin ALT-5 | GPIO5_IO[20] | |||||||
J1.240 | I2C4_SDA | CPU.I2C4_SDA | AD8 | NVCC_3V3 | I/O | Pin ALT-0 | I2C4_SDA | |
Pin ALT-1 | PWM1_OUT | |||||||
Pin ALT-3 | ECSPI2_SS0 | |||||||
Pin ALT-5 | GPIO5_IO[21] | |||||||
J1.242 | DGND | DGND | - | - | G | |||
J1.244 | UART1_RXD | CPU.UART1_RXD | AD6 | NVCC_3V3 | I/O | Pin ALT-0 | UART1_RX | |
Pin ALT-1 | ECSPI3_SCLK | |||||||
Pin ALT-5 | GPIO5_IO[22] | |||||||
J1.246 | UART1_TXD | CPU.UART1_TXD | AJ13 | NVCC_3V3 | I/O | Pin ALT-0 | UART1_TX | |
Pin ALT-1 | ECSPI3_MOSI | |||||||
Pin ALT-5 | GPIO5_IO[23] | |||||||
J1.248 | UART2_RXD | CPU.UART2_RXD | AF6 | NVCC_3V3 | I/O | Pin ALT-0 | UART2_RX | |
Pin ALT-1 | ECSPI3_MISO | |||||||
Pin ALT-3 | GPT1_COMPARE3 | |||||||
Pin ALT-5 | GPIO5_IO[24] | |||||||
J1.250 | UART2_TXD | CPU.UART2_TXD | AH4 | NVCC_3V3 | I/O | Pin ALT-0 | UART2_TX | |
Pin ALT-1 | ECSPI3_SS0 | |||||||
Pin ALT-3 | GPT1_COMPARE2 | |||||||
Pin ALT-5 | GPIO5_IO[25] | |||||||
J1.252 | UART3_RXD | CPU.UART3_RXD | AE6 | NVCC_3V3 | I/O | Pin ALT-0 | UART3_RX | |
Pin ALT-1 | UART1_CTS_B | |||||||
Pin ALT-2 | USDHC3_RESET_B | |||||||
Pin ALT-3 | GPT1_CAPTURE2 | |||||||
Pin ALT-4 | CAN2_TX | |||||||
Pin ALT-5 | GPIO5_IO[26] | |||||||
J1.254 | UART3_TXD | CPU.UART3_TXD | AJ4 | NVCC_3V3 | I/O | Pin ALT-0 | UART3_TX | |
Pin ALT-1 | UART1_RTS_B | |||||||
Pin ALT-2 | USDHC3_VSELECT | |||||||
Pin ALT-3 | GPT1_CLK | |||||||
Pin ALT-4 | CAN2_RX | |||||||
Pin ALT-5 | GPIO5_IO[27] | |||||||
J1.256 | UART4_RXD | CPU.UART4_RXD | AJ15 | NVCC_3V3 | I/O | Pin ALT-0 | UART4_RX | |
Pin ALT-1 | UART2_CTS_B | |||||||
Pin ALT-2 | PCIE_CLKREQ_B | |||||||
Pin ALT-3 | GPT1_COMPARE1 | |||||||
Pin ALT-4 | I2C6_SCL | |||||||
Pin ALT-5 | GPIO5_IO[28] | |||||||
J1.258 | UART4_TXD | CPU.UART4_TXD | AH5 | NVCC_3V3 | I/O | Pin ALT-0 | UART4_TX | |
Pin ALT-1 | UART2_RTS_B | |||||||
Pin ALT-3 | GPT1_CAPTURE1 | |||||||
Pin ALT-4 | I2C6_SDA | |||||||
Pin ALT-5 | GPIO5_IO[29] | |||||||
J1.260 | DGND | DGND | - | - | G |
(*) SPIDF and ISP signals cannot be present at the same time. ISP signals are in alternative to NAND and eMMC usage (see i.MX8Plus NAND controller on Reference Manual for more details). Please contact sales for more information
(**) SAI5 and SE050 ISO interface cannot be present at the same time. Please contact sales for more information
Power and resetEdit
Power Supply Unit (PSU) and recommended power-up sequenceEdit
Implementing correct power-up sequence for iMX8MPlus processors is not a trivial task because several power rails are involved.
ORCA SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
The PSU is composed of two main blocks:
- power management integrated circuit
- additional generic power management circuitry that completes PMIC functionalities
The PSU:
- generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals
- synchronizes the powering up of carrier board in order to prevent back power
Power-up sequenceEdit
The typical power-up sequence is the following:
- 3.3VIN main power supply rail is powered
- SNVS domain signals are pulled-up (unless carrier board circuitry keeps this signal low for any reason)
- CPU_PORn (active-low) is driven low by PMIC
- RTC_RESET_B are internally released after 200ms
- PMIC initiates power-up sequence needed by iMX8M processor
- BOARD_PGOOD goes up when NVCC_3V3 (CPU I/O power rail) is ready
- CPU_PORn is deasserted after the last regulator to bring the processor out of reset
Note on BOARD_PGOOD usageEdit
BOARD_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals.
Depending on the kind of such loads, BOARD_PGOOD might not be able to drive them properly because it has a 20mA output current absolute maximum rating.
In these cases a simple 2-input AND port with a level shifter for the PMIC_RST_B input can be used to address this issue. The following picture depicts a principle schematic showing this solution.
SOM_VDD denotes the power rail used to power ORCA SoM (i.e. 3V3VIN).
Additionally, we suggest using ICs with Schmitt trigger input ports.
Reset scheme and control signalsEdit
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
NVCC_VSNVS_1V8Edit
Some signals that are related to reset circuitry are pulled-up to NVCC_VSNVS_1V8 (1.8V internal rail).
Hence it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.
PMIC_RST_BEdit
EXT_RESET is internally pulled-up with a 100kΩ to NVCC_VSNVS_1V8. Connect EXT_RESET signal to GND (for example with a button or an open-collector circuit) causes the PMIC to assert its POR_B output.
When this signal is pulled low all the power supplies except for the SNVS domain will be OFF.
The RESETn will keep asserted for 250 ms after PMIC_RST_B is released, thus providing enough time for the power supplies to be completely powered down. During this time, the CPU_PORb driven by the PMIC will also keep asserted (low).
After RESETn is released, the power supplies will start to ramp up in defined sequence. When all the power supplies have reached their operating voltages, POR_B will be de-asserted, and the CPU may begin booting from reset.
PMIC_ON_REQ//VMON_RSTEdit
Two different routing options are available for this pin.
By default, this pin is connected to PMIC's PMIC_ON_REQ signal. The PMIC_ON_REQ signal is driven by iMX8MPlus SoC to place the system in power-down mode.
Optionally, PMIC_ON_REQ//VMON_RST can be routed to the master reset input of a voltage supervisor instead. For more details about this option, please write to the Sales Department.
CPU_PORnEdit
PMIC can assert this active-low signal. Other internal IC, such as ethernet PHY or boot memory devices, could be connected to this signal. This guarantees that they are in a known state when reset signal is released.
CPU_ONOFFEdit
CPU_ONOFF is internally pulled-up with a 100kΩ to NVCC_VSNVS_1V8. This input signal is connected directly to the ONOFF input of the CPU.
BOARD_PGOODEdit
BOARD_PGOOD is the output of the voltage monitor on the internal NVCC_3V3 rail (I/O pins supply) and must be used as power enable for all the electronics on MITO 8M carrier board.
When the I/O pins power rail on MITO 8M is not ready (BOARD_PGOOD low) all the integrated circuits connected to the CPU must be powered off in order to avoid back-powering or other issue related to a wrong power-up sequence.
BOOT_MODE_[0-2]Edit
BOOT_MODE_x pins can be internally pulled-up with 10kΩ to NVCC_3V3 or pulled-down with 10kΩ to DGND to provide the default boot mode. The previous block diagram shows the SD3 eMMC boot option.
To overwrite the boot configuration these pins can be pulled low or high with 1kΩ resistor, the pull-up rail has to be a 3.3V enabled by BOARD_PGOOD signal.
WDOG_BEdit
WDOG_B is a PMIC input signal that is configured by default to generate a system reset. It is internally connected to processor's watchdog output.
Handling CPU-initiated software resetEdit
By default, ORCA SOM implements a conservative approach regarding CPU-initiated software reset. In essence, whenever a software reset is issued, a full power-up cycle is triggered. This technique is implemented in DESK-MX8M-L. At the software level, U-Boot and Linux kernel software reset routines make use of a SOC's WDT to assert the WDOG1_WDOG_B reset signal. This signal in turn is routed to GPIO1_IO02 pad (MUX mode = 1, internal connection only). At the hardware level, this signal is connected to the PMIC WDOG_B input to achieve the desired outcome.
System bootEdit
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:
- determines whether the boot is secure or non-secure
- performs some initialization of the system and clean-ups
- reads the mode pins to determine the primary boot device
- once it is satisfied, it executes the boot code
Boot optionsEdit
Many options are available related for ORCA SOM System boot. They are selected by the BOOT_MODE[0..2] signals as reported in the following table:
BOOT_MODE_2 | BOOT_MODE_1 | BOOT_MODE_0 | BOOT peripheral |
---|---|---|---|
0 | 0 | 0 | Boot From Internal Fuses |
0 | 0 | 1 | USB Serial Download |
0 | 1 | 0 | USDHC3 (eMMC boot only, SD3 8-bit) |
0 | 1 | 1 | USDHC2 (SD boot only, SD2) |
1 | 0 | 0 | NAND 8-bit single device 256 page |
1 | 0 | 1 | NAND 8-bit single device 512 page |
1 | 1 | 0 | QSPI 3B Read |
When the signals are left floating the primary boot device is set by default to eMMC on SD3.
The BOOT_MODE[0..2] signals are latched when processor reset is released.
The boot process is managed by on-chip boot ROM code: please refer to the processor's Reference Manual for more information.
On board JTAG connectorEdit
JTAG signals are routed to the J1 primary connector of the ORCA PCB. See the pinout section for more details.
PeripheralsEdit
Electrical, Thermal and Mechanical FeaturesEdit
Operational characteristicsEdit
Maximum ratingsEdit
Parameter | Min | Typ | Max | Unit |
---|---|---|---|---|
Main power supply voltage | 0 | 3.3 | 3.6 | V |
Recommended ratingsEdit
Parameter | Min | Typ | Max | Unit |
---|---|---|---|---|
Main power supply voltage | 3.135 | 3.3 | 3.465 | V |
Power consumptionEdit
Providing theoretical maximum power consumption value would be useless for the majority of system designers building their application upon ORCA module. Practically speaking, these figures would be of no help when it comes to size power supply unit or to perform thermal design of real systems.
Instead, several configurations have been tested in order to provide figures that are measured on real-world use cases.
Please note that ORCA platform is so flexible that it is virtually impossible to test for all possible configurations and applications on the market. The use cases here presented should cover most of real-world scenarios. However actual customer's application might require more power than values reported here or customer's use case may be differ significantly with respect to the ones here considered.
Therefore, application-specific requirements have always to be taken into consideration in order to size power supply unit and to implement thermal management properly.
Use cases resultsEdit
Measurements have been performed on the ORCA SOM under test is equipped with:
- i.MX8MPlus (p.n. MIMX8ML8CVNKZAB)
- 8 GB DDR4LP SDRAM
- 8 GB eMMC
1 Gbps Ethernet link has been always active during the test.
The table below reports the power consumption measurements for the considered use cases.
Section not completed yet |
Checkpoint | Power (mW) |
---|---|
U-boot prompt | TBD |
Linux prompt | TBD |
Stress App test (*) | TBD |
(*) Stressful Application Test: TBD
Thermal managementEdit
The ORCA SOM is designed to support the maximum available temperature range declared by the manufacturer.
The customer shall define and conduct a reasonable number of tests and verification in order to qualify the DUT capabilities to manage the heat dissipation.
Any heatsink, fan etc shall be defined case by case.
DAVE Embedded Systems' team is available for any additional information, please contact sales@dave.eu.
A general overview snapshotEdit
For your information, please see below a snapshot in stress conditions (with about 10W power consumption) with a standard heatsink on top of SOC:
Software thermal protectionEdit
Section not completed yet |
Mechanical specificationsEdit
This chapter describes the mechanical characteristics of the ORCA module.
Board LayoutEdit
The following figure shows the physical dimensions of the ORCA module:
ConnectorsEdit
The following figure shows the ORCA connector layout:
CAD drawingsEdit
- DXF (2D): CS073021.dxf
- STEP (3D): CS073021.step
3D drawingsEdit