Difference between revisions of "Creating and building example Vivado project (BELK/BXELK)"

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{{Applies To Bora}}
 
{{Applies To Bora}}
 
{{Applies To BoraX}}
 
{{Applies To BoraX}}
−
{{Applies To BoraLite}}
 
 
{{InfoBoxBottom}}
 
{{InfoBoxBottom}}
−
 
−
{{ImportantMessage|text=In this document, the Vivado installation path may be indicated as <code>vivado_201x.y</code>. Just replace <code>x</code> and <code>y</code> with the actual numbers of your version. For instance, use the string <code>vivado_2014.4</code> if you are working with Vivado 2014.4.
 
−
}}
 
−
 
  
 
== History ==
 
== History ==
Line 13: Line 8:
 
!Version
 
!Version
 
!Date
 
!Date
−
!BELK/BXELK version
+
!BELK version
 
!Notes
 
!Notes
 
|-
 
|-
Line 20: Line 15:
 
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|3.0.0]]
 
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|3.0.0]]
 
|First release
 
|First release
−
|-
 
−
|2.0.0
 
−
|July 2017
 
−
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|3.0.0, 4.0.0]]
 
−
|Updates for BELK 4.0.0 / BXELK 2.0.0
 
−
|-
 
−
|{{oldid|9008|2.0.1}}
 
−
|September 2019
 
−
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|3.0.0, 4.0.0]]
 
−
|Clarified U-Boot rebuild requirement<br>
 
−
Added ''Downloading the bitstream to the device'' section
 
−
|-
 
−
|3.0.0
 
−
|December 2019
 
−
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|4.1.0, 2.1.0]]
 
−
|
 
 
|-
 
|-
 
|}
 
|}
  
−
<section begin=BELK/>
+
==Command line based procedure==
−
==Creating and building example Vivado project==
+
It is assumed that the development environment has been set up properly as described [[Build_system_(BELK)|here]].
−
BELK/BXELK provides an example Vivado project for BORA/BORAX/BORALITE boards. This project allows to:
 
−
*generate the PS configuration files to be used with U-boot SPL build
 
−
*generate the bitstream of a simple PL design used to route PS' CAN0 and UART0 signals through EMIO (see also the following pictures).
 
−
 
 
−
 
 
−
[[File:Belk-default-vivado-project.png|thumb|center|400px|Block diagram of BORA example project]]
 
−
[[File:Belk-borax-default-vivado-project.png|thumb|center|400px|Block diagram of BORAX example project]]
 
−
[[File:Boralite-default-vivado-project.png|thumb|center|400px|Block diagram of BORALITE example project]]
 
−
 
 
−
This article describes how two build this project. Two procedures are described, the former is command line based while the latter is GUI based.
 
−
 
 
−
The project is stored is a git repository, as described [[BORA_SOM/BELK-L/Development/Build_system#Setting_up_the_Zynq_development_server_environment|here]].
 
−
 
 
−
It is assumed that the Zynq development environment has been set up properly (see [[BORA_SOM/BELK-L/Development/Build_system|this page]] for more details).
 
−
 
 
−
===Command line based procedure===
 
−
{{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>
 
−
Define the correct ones according the target SoM.<br>
 
−
For Bora SoM use:
 
−
*<code>export BASE_NAME=bora</code>
 
−
*<code>export UBOOT_PS7_DIR=bora</code>
 
−
For BoraLite SoM use:
 
−
*<code>export BASE_NAME=boralite</code>
 
−
*<code>export UBOOT_PS7_DIR=bora</code>
 
−
For BoraX SoM use:
 
−
*<code>export BASE_NAME=borax</code>
 
−
*<code>export UBOOT_PS7_DIR=borax</code>
 
−
}}
 
−
 
 
  
 
*start the Zynq development server and login into the system
 
*start the Zynq development server and login into the system
 
*assuming that a local repository has not been created, clone the remote BORA git repository:
 
*assuming that a local repository has not been created, clone the remote BORA git repository:
 
*:<code>git clone git@git.dave.eu:dave/bora/bora.git</code>
 
*:<code>git clone git@git.dave.eu:dave/bora/bora.git</code>
−
*copy the <code><bora_repo>/boards/</code> directory to <code><vivado_install_dir>/data/boards/</code>  
+
*copy the <code><bora_repo>/boards/board_parts/zynq/BELK_2.2.0</code> directory to <code><vivado_2014.4_install_dir>/data/boards/board_parts/zynq/</code> :
 
<pre>
 
<pre>
 
cd <bora_repo>
 
cd <bora_repo>
−
sudo cp -r boards/ /opt/Xilinx/Vivado/<Vivado_version>/data/
+
sudo cp -r boards/board_parts/zynq/BELK_2.2.0 /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/
 
</pre>
 
</pre>
−
*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/<Vivado_version>/settings32.sh</code>}}{{efn|Passing the -tclargs "gen_bitstream" parameters allows for automatic building of the FPGA bitstream.}}:
+
*enter the git directory and launch the following command
 +
*:<code>export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk</code>
 +
*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014.4/settings32.sh</code>}}:
 
<pre>
 
<pre>
−
. /opt/Xilinx/Vivado/<Vivado_version>/settings64.sh
+
. /opt/Xilinx/Vivado/2014.4/settings64.sh1
−
vivado -mode tcl -source scripts/recreate_prj_${BASE_NAME}_BASE.tcl -notrace -tclargs "gen_bitstream"
+
vivado -mode tcl -source build_project.tcl -notrace -tclargs "-bitstream"
 
</pre>
 
</pre>
−
*At the end of the bitstream build process, the <code>build_prj_*</code> script allows to automatically export hardware and lauch SDK.
+
*at the end of the bitstream build process, the <code>build_project</code> script allows to automatically export hardware and lauch SDK to build the FSBL
−
*The bitstream file is now present in <code><bora_repo>/vivado/${BASE_NAME}.runs/impl_1/${BASE_NAME}_wrapper.bit</code> and <code><bora_repo>/vivado/${BASE_NAME}.runs/impl_1/${BASE_NAME}_wrapper.bin</code>.
+
*once the Xilinx SDK is ready, perform the following operations from the GUI:
−
*By default FSBL is not used anymore in the boot process. U-Boot SPL (first-stage bootloader) is used instead. PS configuration files are used to build U-boot binaries.
+
**Click on ''File -> New -> Application Project''
−
**Copy the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files into U-boot source code directory using the following command example for Bora:
+
**Select the Project Name: ''bora_FSBL''
−
:<code>cp <bora_repo>/bd/${BASE_NAME}/ip/${BASE_NAME}_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/${UBOOT_PS7_DIR}/</code>
+
**Click ''Next''
−
:*Follow [[BORA_SOM/BELK-L/Development/Building_U-Boot | U-boot build instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files generated by the Vivado project described in this article'''. As such, it is not generally required to rebuild U-Boot.
+
**Select ''Template: Zynq FSBL''
−
:**The PS configurations are the same for Bora and BoraLite boards.
+
**Click on ''Finish''
−
 
+
**Apply the patch, right-clicking on ''bora_FSBL'' in Project Explorer and then by clicking on ''Team -> Apply Patch..''
−
===GUI based procedure===
+
**From ''Browse...'' open the file <code><bora_repo>/patch/belk-sd-boot.patch</code>
−
{{ImportantMessage|text=The following procedure make use of ambient variables to address all our boards.<br>
+
**Click ''Next''
−
Define the correct ones according the target SoM.<br>
+
**Select ''Apply the patch to the selected file, folder or project:'' and select <code>main.c</code> from ''bora_FSBL -> src''
−
For Bora SoM use:
+
**Click ''Next''
−
*<code>export BORA_SOM=Bora</code>
+
**Check that the patch is correctly applied to the source code and click on ''Finish''
−
*<code>export BASE_NAME=bora</code>
+
*the FSBL (ELF file) is built automatically
−
*<code>export UBOOT_PS7_DIR=bora</code>
+
*create the binary from the FSBL ELF chosing one of the following options:
−
For BoraLite SoM use:
+
**launch this command manually <code>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin</code>
−
*<code>export BORA_SOM=BoraLite</code>
+
**configure the automatic binary generation on project build. In Project Explorer, right-click on ''bora_FSBL'' project, select C/C++ Build Settings and add the command <code>arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin</code> on ''Post-build steps''
−
*<code>export BASE_NAME=boralite</code>
+
*create the <code>BOOT.bin</code> image (single file including FSBL, FPGA and U-boot for uSD boot:
−
*<code>export UBOOT_PS7_DIR=bora</code>
+
**select the ''bora_FSBL project'' in ''Project Explorer''
−
For BoraX SoM use:
+
**click on ''Xilinx Tools -> Create Zynq Boot Image''
−
*<code>export BORA_SOM=BoraX</code>
+
*if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add U-Boot to the list
−
*<code>export BASE_NAME=borax</code>
+
*otherwise, select Create new BIF file and set the output path and in Boot image partitions add the following files:
−
*<code>export UBOOT_PS7_DIR=borax</code>
+
**<code>bora_FSBL.elf</code>, which can be found in the project Debug directory. N.B. check that the <u>Partition Type for FSBL is bootloader</u>
−
}}
+
**<code>bora_wrapper.bit</code>, which is the bitstream generated by the Vivado project (<u>Partition Type must be Datafile</u>)
−
 
+
**<code>u-boot.elf</code>, which is the compiled U-Boot with .elf extension (<u>Partition Type must be Datafile</u>)
 +
*in ''Output path'', select the path for the <code>BOOT.bin</code> file.
  
 +
==GUI based procedure==
 +
It is assumed that the development environment has been set up properly as described [[Build_system_(BELK)|here]].
 
*start the Zynq development server and login into the system
 
*start the Zynq development server and login into the system
 
*assuming that a local repository has not been created, clone the remote BORA git repository:<code>git clone git@git.dave.eu:dave/bora/bora.git</code>
 
*assuming that a local repository has not been created, clone the remote BORA git repository:<code>git clone git@git.dave.eu:dave/bora/bora.git</code>
−
 
+
*copy the <code><bora_repo>/boards/board_parts/zynq/BELK_2.2.0</code> directory to <code><vivado_2014.4_install_dir>/data/boards/board_parts/zynq/</code> :
−
*copy the <code><bora_repo>/boards/</code> directory to <code><vivado_install_dir>/data/boards/</code> :
 
 
<pre>
 
<pre>
 
cd <bora_repo>
 
cd <bora_repo>
−
sudo cp -r boards/ /opt/Xilinx/Vivado/<Vivado_version>/data/
+
sudo cp -r boards/board_parts/zynq/BELK_2.2.0 /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/
 
</pre>
 
</pre>
−
*launch the Vivado Design Suite GUI with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/201x.y/settings32.sh</code>}}:
+
*launch Vivado v2014.4 and from the start page click on ''Create New Project''
−
<pre>
 
−
. /opt/Xilinx/Vivado/201x.y/settings64.sh
 
−
vivado
 
−
</pre>
 
−
*from the start page click on ''Create New Project''
 
 
*click ''Next''
 
*click ''Next''
−
*select the directory build project, insert the name of the project ''<prj_name>'' and click ''Next''
+
*select the directory build project, insert the name of the project ''Project Name'' and click ''Next''
 
*select ''RTL Project'', enable ''Do not specify sources at this time'' and click ''Next''
 
*select ''RTL Project'', enable ''Do not specify sources at this time'' and click ''Next''
−
*on the ''Default Part'' form, click on the ''Boards'' button to filter the available boards. Select ''${BORA_SOM}'' and click ''Next''
+
*on the ''Default Part'' form, click on the ''Boards'' button to filter the available boards. Select ''BELK 2.2.0'' and click ''Next''
 
*check the summary page and click ''Finish''
 
*check the summary page and click ''Finish''
−
*For the block design there are two possible ways:
+
*in the Vivado GUI click on ''Create Block Design'' from the ''Flow Navigator''
−
**Add the existing BD within the repo:
+
*insert ''bora'' as ''Design name'' and click ''OK''
−
***select ''Add sources''  from the ''Flow Navigator''
+
*this creates a new block design. From the Diagram tab, add a new IP:
−
***click on ''Add or create design sources''
+
**click the ''Add IP'' side button, or
−
***select Add Files and add <code><bora_repo>/bd/${BASE_NAME}/${BASE_NAME}.bd</code>
+
**click ''Add IP'' on the upper suggestions bar
−
***check that the option ''Copy sources into project'' is disabled and click finish
+
*double click on ''ZYNQ7 Processing System''
−
**Create a new block design:
+
*this adds the IP that models the PL component of Zynq. Launch ''Run Block Automation'' from the upper suggestions bar
−
***click on ''Create Block Design'' from the ''Flow Navigator''
+
*check that ''Apply Board Preset'' is selected and click ''OK''
−
***insert ''${BASE_NAME}'' as ''Design name'' and click ''OK''
+
*this applies the default settings for BORA and creates the I/O ports for the DDR and MIO pins and for the UART_0 and CAN_0 interfaces
−
***this creates a new block design. From the Diagram tab, add a new IP:
+
*manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design
−
****click the ''Add IP'' side button, or
+
*from the sources tab, select the BORA block design (<code>bora.bd</code>) as ''Design Sources'' and from the context menu select ''Create HDL Wrapper''
−
****click ''Add IP'' on the upper suggestions bar
+
*on the next window, select ''Copy generated wrapper'' to allow user edits and click ''OK''
−
***double click on ''ZYNQ7 Processing System''
+
*this creates the Verilog <code>bora_wrapper.v</code> file. If this file is not automatically included in the project, add it using the ''Add sources'' option
−
***this adds the IP that models the PL component of Zynq. Launch ''Run Block Automation'' from the upper suggestions bar
+
**select Add or create design sources and click ''Next''
−
***check that ''Apply Board Preset'' is selected and click ''OK''
+
**select the <code>bora_wrapper.v</code> file from the <code><prj_name>.srcs/sources_1/bd/bora/hdl/</code> directory
−
****this applies the default settings for BORA/BORAX and creates the I/O ports for the DDR and MIO pins
 
−
***UART_0 and CAN_0 connections must be manually created:
 
−
****right-clicking on each port (where mouse cursor switch to ''pencil'') and selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>. The name of the external ports must be UART_0 and CAN_0 respectively, otherwise correct manually
 
−
***manually connect the <code>FCLK_CLK0</code> signal to <code>M_AXI_GP0_ACLK</code> and save the block design
 
−
***from the sources tab, select the BORA block design <code>${BASE_NAME}.bd</code> as ''Design Sources'' and from the context menu select ''Create HDL Wrapper''
 
−
***on the next window, select ''Let Vivado menage wrapper and auto-update'' and click ''OK''
 
−
***this creates the Verilog file <code>${BASE_NAME}_wrapper.v</code>. If this file is not automatically included in the project, add it using the ''Add sources'' option
 
−
****select Add or create design sources and click ''Next''
 
−
****select the <code>>${BASE_NAME}_wrapper.v</code> file from the <code><project_directory>/<prj_name>.srcs/sources_1/bd/${BASE_NAME}/hdl/</code> directory
 
−
 
 
 
*select ''Add sources'' and click on ''Add or create constraints''
 
*select ''Add sources'' and click on ''Add or create constraints''
−
*select the <code>${BASE_NAME}_pinout.xdc</code> and <code>${BASE_NAME}_timings.xdc</code> files from the <code>constr</code> directory of the BORA repository
+
*select the <code>bora_pinout.xdc</code> and <code>bora_timings.xdc</code> files from the <code>constr</code> directory of the BORA repository
−
*check that the option ''Copy constraints'' ''files into project'' is disabled and click finish
+
*check that the option ''Copy constraints'' files into project is enabled
 
*create the synthesis, implementation and bitstream clicking ''Generate Bitstream'' from the ''Flow Navigator'' and wait the completion of the operation
 
*create the synthesis, implementation and bitstream clicking ''Generate Bitstream'' from the ''Flow Navigator'' and wait the completion of the operation
 
*once completed, select ''Open Implemented Design''
 
*once completed, select ''Open Implemented Design''
 
*create the binary bitstream running the tcl script provided with the BORA repository. Launch ''Tools -> Run Tcl Script''
 
*create the binary bitstream running the tcl script provided with the BORA repository. Launch ''Tools -> Run Tcl Script''
−
*select the <code>generate_binary_bitstream.tcl</code> file from the <code>scripts</code> directory from the BORA repository
+
*select the <code>generate_binary_bitstream.tcl</code> file from the scripts directory from the BORA repository
−
*The bitstream file is now present in <code><project_directory>/<prj_name>.runs/impl_1/${BASE_NAME}_wrapper.bit</code> and <code><project_directory>/<prj_name>.runs/impl_1/${BASE_NAME}_wrapper.bin</code>.
+
*select ''File -> Export -> Export Hardware''
−
*Copy the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files into U-boot source code directory using the following command example for Bora:
+
*on the next window, enable ''Include Bitstream'' and click ''OK''
−
:<code>cp <project_directory>/<prj_name>.srcs/sources_1/bd/${BASE_NAME}/ip/<prj_name>_processing_system7_0_0/ps7_init_gpl.* <U-boot_src_dir>/board/dave/bora/${UBOOT_PS7_DIR}/</code>Follow [[BORA_SOM/BELK-L/Development/Building_U-Boot | U-boot build instructions]] to build U-boot using new PS configurations. '''Please note that the U-Boot binary images released along with BELK/BXELK were already built upon the <code>ps7_init_gpl.c</code> and <code>ps7_init_gpl.h</code> source files generated by the Vivado project described in this article'''. As such, it is not generally required to rebuild U-Boot.
+
*now launch the SDK session to generate the FSBL, clicking on ''File -> Launch SDK''
−
-----
+
*once the Xilinx SDK is ready, perform the following operations from the GUI:
−
{{notelist}}
+
**Click on ''File -> New -> Application Project''
−
 
+
**Select the Project Name: <code>bora_FSBL</code>
−
=== Downloading the bitstream to the device ===
+
**Click Next
−
Once the bitstream is ready, U-Boot itself can be used to download it onto the device. There are other options, however. For more details, please refer to [[BELK-AN-008:_Programming_the_FPGA_Bitstream_with_U-Boot#Introduction|this section]].
+
**Select Template: Zynq FSBL
−
 
+
**Click on Finish
−
=== Helloworld from UART0 ===
+
**Apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply Patch..
−
Using the FPGA bitstream previously created, it is possible to use serial tty port on Linux. The serial port is mapped to <code>/dev/ttyPS1</code> (this is because <code>/dev/ttyPS0</code> is the console mapped to UART1).
+
*From Browse... open the file <code><bora_repo>/patch/belk-sd-boot.patch</code>
−
 
+
**Click Next
−
Here below an example on C code for initializing and using UART0 through FPGA:
+
**Select ''Apply the patch to the selected file, folder or project'': and select <code>main.c</code> from ''bora_FSBL -> src''
−
 
+
**Click ''Next''
−
<pre>
+
**Check that the patch is correctly applied to the source code and click on ''Finish''
−
#include <stdio.h>
+
*the FSBL (ELF file) is built automatically
−
#include <stdlib.h>
+
*create the binary from the FSBL ELF chosing one of the following options:
−
#include <string.h>
+
**manually launch the command: <code>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin</code>
−
#include <errno.h>
+
**configure the automatic binary generation on project build. In ''Project Explorer'', right-click on <code>bora_FSBL</code> project and select ''C/C++ Build Settings'' and add the command <code>arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin</code> on ''Post-build steps''
−
#include <fcntl.h>
+
*create the <code>BOOT.bin</code> image (single file including FSBL, FPGA and U-boot for uSD boot:
−
#include <termios.h>
+
**select the <code>bora_FSBL</code> project in ''Project Explorer''
−
 
+
**click on ''Xilinx Tools -> Create Zynq Boot Image''
−
int set_interface_attribs (int fd, int speed, int parity)
+
*if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add U-Boot to the list.  
−
{
+
*otherwise, select ''Create new BIF file'' and set the output path and in ''Boot image partitions'' add the following files:
−
        struct termios tty;
+
**bora_FSBL.elf, which can be found in the project <code>Debug</code> directory. N.B. check that the ''Partition Type'' for FSBL is ''bootloader''
−
        memset (&tty, 0, sizeof tty);
+
**<code>bora_wrapper.bit</code>, which is the bitstream generated by the Vivado project (''Partition Type'' must be ''Datafile'')
−
        if (tcgetattr (fd, &tty) != 0)
+
**<code>u-boot.elf</code>, which is the compiled U-Boot with <code>.elf</code> extension (''Partition Type'' must be ''Datafile'')
−
        {
+
*in ''Output path'', select the path for the <code>BOOT.bin</code> file
−
                printf("error %d from tcgetattr", errno);
 
−
                return -1;
 
−
        }
 
−
 
 
−
        cfsetospeed (&tty, speed);
 
−
        cfsetispeed (&tty, speed);
 
−
 
 
−
        tty.c_cflag = (tty.c_cflag & ~CSIZE) | CS8;    // 8-bit chars
 
−
        // disable IGNBRK for mismatched speed tests; otherwise receive break
 
−
        // as \000 chars
 
−
        tty.c_iflag &= ~IGNBRK;        // disable break processing
 
−
        tty.c_lflag = 0;                // no signaling chars, no echo,
 
−
                                        // no canonical processing
 
−
        tty.c_oflag = 0;                // no remapping, no delays
 
−
        tty.c_cc[VMIN]  = 0;            // read doesn't block
 
−
        tty.c_cc[VTIME] = 5;            // 0.5 seconds read timeout
 
−
 
 
−
        tty.c_iflag &= ~(IXON | IXOFF | IXANY); // shut off xon/xoff ctrl
 
−
 
 
−
        tty.c_cflag |= (CLOCAL | CREAD);// ignore modem controls,
 
−
                                        // enable reading
 
−
        tty.c_cflag &= ~(PARENB | PARODD);      // shut off parity
 
−
        tty.c_cflag |= parity;
 
−
        tty.c_cflag &= ~CSTOPB;
 
−
        tty.c_cflag &= ~CRTSCTS;
 
−
 
 
−
        if (tcsetattr (fd, TCSANOW, &tty) != 0)
 
−
        {
 
−
                printf("error %d from tcsetattr", errno);
 
−
                return -1;
 
−
        }
 
−
        return 0;
 
−
}
 
−
 
 
−
 
 
−
int main()
 
−
{
 
−
int fd;
 
−
char *portname = "/dev/ttyPS1";
 
−
 
 
−
char msg[] = "Hello World from BELK (FPGA PS0 UART)!\n\r";
 
−
 
 
−
fd = open(portname, O_RDWR | O_NOCTTY | O_SYNC);
 
−
if (fd < 0)
 
−
{
 
−
        printf("error %d opening %s: %s", errno, portname, strerror (errno));
 
−
        exit(1);
 
−
}
 
−
printf(msg);
 
−
 
 
−
set_interface_attribs (fd, B115200, 0);  // set speed to 115,200 bps, 8n1 (no parity)
 
−
write(fd, msg, strlen(msg));
 
−
 
 
−
exit(0);
 
−
}
 
−
 
 
−
 
 
−
</pre>
 
−
 
 
−
and then compile it:
 
−
 
 
−
<pre>
 
−
dvdk@vagrant:~/bora/rfs/belk/home/root$ source ~/env.sh
 
−
dvdk@vagrant:~/bora/rfs/belk/home/root$ $CC hello_UART0.c -o hello_UART0
 
−
</pre>
 
−
 
 
−
The program executed print out the msg string on the serial console and on <code>/dev/ttyPS1</code> port.
 
−
<section end=BELK/>
 

Revision as of 15:14, 29 October 2015

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Info Box
Bora5-small.jpg Applies to Bora
BORA Xpress.png Applies to BORA Xpress

History[edit | edit source]

Version Date BELK version Notes
1.0.0 November 2015 3.0.0 First release

Command line based procedure[edit | edit source]

It is assumed that the development environment has been set up properly as described here.

  • start the Zynq development server and login into the system
  • assuming that a local repository has not been created, clone the remote BORA git repository:
    git clone git@git.dave.eu:dave/bora/bora.git
  • copy the <bora_repo>/boards/board_parts/zynq/BELK_2.2.0 directory to <vivado_2014.4_install_dir>/data/boards/board_parts/zynq/ :
cd <bora_repo>
sudo cp -r boards/board_parts/zynq/BELK_2.2.0 /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/
  • enter the git directory and launch the following command
    export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk
  • launch the Vivado Design Suite with the following commands[a]:
. /opt/Xilinx/Vivado/2014.4/settings64.sh1
vivado -mode tcl -source build_project.tcl -notrace -tclargs "-bitstream"
  • at the end of the bitstream build process, the build_project script allows to automatically export hardware and lauch SDK to build the FSBL
  • once the Xilinx SDK is ready, perform the following operations from the GUI:
    • Click on File -> New -> Application Project
    • Select the Project Name: bora_FSBL
    • Click Next
    • Select Template: Zynq FSBL
    • Click on Finish
    • Apply the patch, right-clicking on bora_FSBL in Project Explorer and then by clicking on Team -> Apply Patch..
    • From Browse... open the file <bora_repo>/patch/belk-sd-boot.patch
    • Click Next
    • Select Apply the patch to the selected file, folder or project: and select main.c from bora_FSBL -> src
    • Click Next
    • Check that the patch is correctly applied to the source code and click on Finish
  • the FSBL (ELF file) is built automatically
  • create the binary from the FSBL ELF chosing one of the following options:
    • launch this command manually arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin
    • configure the automatic binary generation on project build. In Project Explorer, right-click on bora_FSBL project, select C/C++ Build Settings and add the command arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin on Post-build steps
  • create the BOOT.bin image (single file including FSBL, FPGA and U-boot for uSD boot:
    • select the bora_FSBL project in Project Explorer
    • click on Xilinx Tools -> Create Zynq Boot Image
  • if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add U-Boot to the list
  • otherwise, select Create new BIF file and set the output path and in Boot image partitions add the following files:
    • bora_FSBL.elf, which can be found in the project Debug directory. N.B. check that the Partition Type for FSBL is bootloader
    • bora_wrapper.bit, which is the bitstream generated by the Vivado project (Partition Type must be Datafile)
    • u-boot.elf, which is the compiled U-Boot with .elf extension (Partition Type must be Datafile)
  • in Output path, select the path for the BOOT.bin file.

GUI based procedure[edit | edit source]

It is assumed that the development environment has been set up properly as described here.

  • start the Zynq development server and login into the system
  • assuming that a local repository has not been created, clone the remote BORA git repository:git clone git@git.dave.eu:dave/bora/bora.git
  • copy the <bora_repo>/boards/board_parts/zynq/BELK_2.2.0 directory to <vivado_2014.4_install_dir>/data/boards/board_parts/zynq/ :
cd <bora_repo>
sudo cp -r boards/board_parts/zynq/BELK_2.2.0 /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/
  • launch Vivado v2014.4 and from the start page click on Create New Project
  • click Next
  • select the directory build project, insert the name of the project Project Name and click Next
  • select RTL Project, enable Do not specify sources at this time and click Next
  • on the Default Part form, click on the Boards button to filter the available boards. Select BELK 2.2.0 and click Next
  • check the summary page and click Finish
  • in the Vivado GUI click on Create Block Design from the Flow Navigator
  • insert bora as Design name and click OK
  • this creates a new block design. From the Diagram tab, add a new IP:
    • click the Add IP side button, or
    • click Add IP on the upper suggestions bar
  • double click on ZYNQ7 Processing System
  • this adds the IP that models the PL component of Zynq. Launch Run Block Automation from the upper suggestions bar
  • check that Apply Board Preset is selected and click OK
  • this applies the default settings for BORA and creates the I/O ports for the DDR and MIO pins and for the UART_0 and CAN_0 interfaces
  • manually connect the FCLK_CLK0 signal to M_AXI_GP0_ACLK and save the block design
  • from the sources tab, select the BORA block design (bora.bd) as Design Sources and from the context menu select Create HDL Wrapper
  • on the next window, select Copy generated wrapper to allow user edits and click OK
  • this creates the Verilog bora_wrapper.v file. If this file is not automatically included in the project, add it using the Add sources option
    • select Add or create design sources and click Next
    • select the bora_wrapper.v file from the <prj_name>.srcs/sources_1/bd/bora/hdl/ directory
  • select Add sources and click on Add or create constraints
  • select the bora_pinout.xdc and bora_timings.xdc files from the constr directory of the BORA repository
  • check that the option Copy constraints files into project is enabled
  • create the synthesis, implementation and bitstream clicking Generate Bitstream from the Flow Navigator and wait the completion of the operation
  • once completed, select Open Implemented Design
  • create the binary bitstream running the tcl script provided with the BORA repository. Launch Tools -> Run Tcl Script
  • select the generate_binary_bitstream.tcl file from the scripts directory from the BORA repository
  • select File -> Export -> Export Hardware
  • on the next window, enable Include Bitstream and click OK
  • now launch the SDK session to generate the FSBL, clicking on File -> Launch SDK
  • once the Xilinx SDK is ready, perform the following operations from the GUI:
    • Click on File -> New -> Application Project
    • Select the Project Name: bora_FSBL
    • Click Next
    • Select Template: Zynq FSBL
    • Click on Finish
    • Apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply Patch..
  • From Browse... open the file <bora_repo>/patch/belk-sd-boot.patch
    • Click Next
    • Select Apply the patch to the selected file, folder or project: and select main.c from bora_FSBL -> src
    • Click Next
    • Check that the patch is correctly applied to the source code and click on Finish
  • the FSBL (ELF file) is built automatically
  • create the binary from the FSBL ELF chosing one of the following options:
    • manually launch the command: arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin
    • configure the automatic binary generation on project build. In Project Explorer, right-click on bora_FSBL project and select C/C++ Build Settings and add the command arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin on Post-build steps
  • create the BOOT.bin image (single file including FSBL, FPGA and U-boot for uSD boot:
    • select the bora_FSBL project in Project Explorer
    • click on Xilinx Tools -> Create Zynq Boot Image
  • if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add U-Boot to the list.
  • otherwise, select Create new BIF file and set the output path and in Boot image partitions add the following files:
    • bora_FSBL.elf, which can be found in the project Debug directory. N.B. check that the Partition Type for FSBL is bootloader
    • bora_wrapper.bit, which is the bitstream generated by the Vivado project (Partition Type must be Datafile)
    • u-boot.elf, which is the compiled U-Boot with .elf extension (Partition Type must be Datafile)
  • in Output path, select the path for the BOOT.bin file


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