Description and default configuration
An external watchdog timer (WDT), Maxim MAX6373), is connected to the PORSTn signal. During normal operation, the microprocessor should repeatedly toggle the watchdog input WDI before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset the μP.
Default mounting option is depicted in the following figure.
WDI is connected to Zynq's PS_MIO15_500 I/O. This signal is available on Bora connectors as PS_MIO15_500 (J1.133).
MAX6373 timeout is pin-selectable. It can be configured through the WD_SET0 (J2.100), WD_SET1 (J2.98) and WD_SET2 (J2.96) signals. By default, they are configured as follows:
- WD_SET2 = 1
- WD_SET1 = 1
- WD_SET0 = 0
This set selects the option (the exhaustive list of configurations options is descripted in table 1 of reference ):
- tDELAY = first edge
- tWD = 10s.
In other words, WDT is started when the first transition on WDI input is detected. Once started, its timeout period is 10s. The first transition of WDI input should be under software control. However, despite of the presence of 22kOhm pull-down, during power-on sequence a spurious 0-to-1 transition may be observed on WDI input. The voltage swing of this transition is variable, since it depends on the internal Zynq's pull-up value of PS_MIO15_500 pad. In general, WDT may be inadvertently started at power-up, before software takes control of PS_MIO15_500 GPIO. To avoid this situation, it is recommended to add a 2.2kOhm pull-down on carrier board, connected to the PS_MIO15_500 signal.
In any case, when the watchdog is started, the software (bootloader/operating system) must take care of toggling the watchdog trigger pin (WDI) before the timeout expiration.
Selecting different configurations
Since WD_SETx signals are routed externally, WDT configuration can be changed by optional circuitry implemented on the carrier board. Different solutions can be implemented on the carrier board, depending on system requirements. The easiest circuit consists of additional stronger pull-up/down resistors connected to WD_SETx pins in order to overrule default configuration. As MAX6373 allows to change the configuration during operation, more complex solutions can be implemented as well.
Please note that on the BORAEVB carrier board, by default WDT is disabled via S1, S2 and S3 dip switches (WD_SET2=0, WD_SET1=1, WD_SET0=1).
It is also worth mentioning that Zynq integrates a System Watchdog Timer (SWDT) that can optionally generates a reset pulse on PS_MIO15_500 pad if this is configured as SWDT reset. In case such a configuration is of interest, on request MAX6373 may not be populated. For more details about this option, please contact Sales Department.