ETRA SBC/Interfaces and Connectors/AUX

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History
Issue Date Notes
2021/04/06 First release


Auxiliary connectors interface[edit | edit source]

Description[edit | edit source]

The Auxiliary connectors on the Evaluation Kit are J11 and J12, 2x15x2.54mm stripline header.

On these connectors are available many interfaces, some of this peripherals are not available at the same time:

  • FDCAN1
  • FDCAN2
  • I2C5
  • SPI5
  • UART7
  • SAI2
  • 11x8 keyboard matrix
  • LED driver
  • JTAG
Auxiliary connectors

Signals[edit | edit source]

The following tables describe the connectors signals:

  • J11
Pin# SOM Pin# Pin name POWER JTAG KEYBOARD LED
1 - 5V_CB 5V
2 - 3V3_CB 3.3V
3 J18.143 ADP5589_R2 ROW_2
4 J18.149 ADP5589_C0 COLUMN_0 LED_0
5 J18.141 ADP5589_R3 ROW_3
6 J18.151 ADP5589_C1 COLUMN_1 LED_1
7 J18.139 ADP5589_R4 ROW_4
8 J18.155 ADP5589_C2 COLUMN_2 LED_2
9 J18.137 ADP5589_R5 ROW_5
10 J18.157 ADP5589_C3 COLUMN_3 LED_3
11 J18.135 ADP5589_R6 ROW_6
12 J18.159 ADP5589_C4 COLUMN_4 LED_4
13 J18.133 ADP5589_R7 ROW_7
14 J18.161 ADP5589_C5 COLUMN_5 LED_5
15,20,29 - DGND Ground
16 J18.147 ADP5589_R0 ROW_0
17 - VDD 3.3V ref. voltage
18 J18.145 ADP5589_R1 ROW_1
19 J18.90 JTMS-SWDIO JTMS-SWDIO
21 J18.98 JTCK-SWCLK JTCK-SWCLK
22 J18.163 ADP5589_C6 COLUMN_6
23 J18.92 JTDI JTDI
24 J18.165 ADP5589_C7 COLUMN_7
25 J18.96 JTDO-TRACESWOO JTDO-TRACESWOO
26 J18.167 ADP5589_C8 COLUMN_8
27 J18.94 NJTRST NJTRST
28 J18.169 ADP5589_C9 COLUMN_9
30 J18.171 ADP5589_C10 COLUMN_10
  • J12
Pin# SOM Pin# Pin name POWER System control CAN I2C SPI UART SAI
1 - 5V_CB 5V
2,4 - PMIC_3V3 3.3V
3 J18. PD13 SAI2_SCK_A
5 J18. PD12 SAI2_FS_A
6 J18. PB13 FDCAN2_TX
7 J18. PD11 SAI2_SD_A
8 J18. PB5 FDCAN2_RX
9 J18. PG9 SAI2_FS_B
10, 11, 16, 19, 29, 30 - DGND Ground
12 J18. PA12 FDCAN1_TX I2C5_SDA
13 - 3V3_CB 3.3V
14 J18. PA11 FDCAN1_RX I2C5_SCL
15 - N.C.
17 - N.C.
18 J18. PF6 SPI5_NSS UART7_RX
20 J18. PF9 SPI5_MOSI UART7_CTS
21 J18. NRST system reset
22 J18. PF7 SPI5_SCK UART7_TX
23 J18. PONKEYn power key
24 J18. PF8 SPI5_MISO UART7_RTS/

UART7_DE

25 J18. EEPROM_WP write protect for carrier eeprom
26 J18. PD6
27 J18. MEM_WP# write protect for NAND
28 J18. PA9

Device usage[edit | edit source]

CAN[edit | edit source]

The CAN interfaces need a tranceiver to be connected to the CAN bus.

NOTE: the FDCAN1 pins are shared with touchscreen I2C interface and are not available when using I2C5.

See the CAN page for more informations.

I2C5[edit | edit source]

Configured by deafult for touchscreen I2C interface.

See the I2C page for more informations.

SPI5[edit | edit source]

NOTE: these pins are shared with UART7, cannot be used at the same time.

See the SPI page for more informations.

UART7[edit | edit source]

NOTE: these pins are shared with SPI5, cannot be used at the same time.

See the UART page for more informations.

SAI2[edit | edit source]

See the Audio page for more informations.

LED driver[edit | edit source]

Open collector outputs through a 120ohm resistor. Can be drive indicators LEDs

By default all the pins are available.

keyboard matrix[edit | edit source]

NOTE: COLUMN[0:5] are not available by default as the pins are routed to the LED open collector outputs. Please send an e-mail to helpdesk@dave.eu for custom configurations.

See the IO_expander page for more informations.

Interface membrane[edit | edit source]

This mambrane can be provided for user interface when the system is mounted on the 4 modules DIN BAR profile, it can offer up to 2 keys and 6 LEDs.

Please send an e-mail to helpdesk@dave.eu for more informations.

JTAG[edit | edit source]

See the JTAG page for more informations.

System control[edit | edit source]

See the reset scheme for more informations.

The system control signals are the following:

  • system reset
    • tie to ground for reset the system
  • power key
    • tie to ground for power up and down the system
  • write protect for carrier eeprom
    • tie to ground for write inside the carrier eeprom
    • the first 32 bytes of the eeprom are used to store the CB ConfigID, the corruption of these bytes prevents the system from boot.
  • write protect for NAND
    • this pin allow to prevent unwanted writes, tie to ground when the NAND are not to be written.