ETRA SOM/ETRA Hardware/Power and Reset/Reset scheme and control signals

History
Issue Date	Notes
2020/12/30	First Release

Reset scheme and control signals

The following picture shows the simplified block diagram of reset scheme and voltage monitoring.

VDD

Some signals that are related to reset circuitry are pulled-up to VDD rail. This voltage is generated by the PMIC and act as power good to switch on/off the all the peripheral that could back power the CPU.

NRST

Open drain rest signal, tie to DGND to reset the system.

It is driven by:

• the PMIC to force the CPU in reset state
• the CPU over a soft reset to restart the application

This signal is also used to reset the following on board peripherals:

• SPI NOR
• eMMC

SOM_PGOOD

This is a convencional signal to drive DC/DC enable inputs or switch on/off control signals. It is connected to the VDD through a 22Ohm resistor.

PONKEYn

User power on key (active low with internal pull-up), used to wake up the sysytem from power down.

NRST_CORE

Reset signal for the core, to be used if the VDD_CORE is not disabled during the reset. Internally tied to NRST signal.

PWR_ON

Power on CPU output signal, The state of this signal depends on power state of the processor.

PDR_ON

Input pin that disables the VDD internal voltage monitor. When this signal is set to logic 1 the processor does not issue a reset cycle when the VDD goes below the VVD_OK threshold.

Driven by default by PMIC, internally used for deep sleep modes.

PDR_ON_CORE

Input pin that disables the VDD_CORE internal voltage monitor. When this signal is set to logic 1 the processor does not issue a core reset cycle when the VDD_CORE goes below the VVD_OK threshold.

Driven by default by PMIC, internally used for deep sleep modes.

PWR_LP

CPU low power mode output, internally used by the PMIC to check the CPU low power state.

WAKEUP

PMIC power on signal from CPU, used in low power mode by the CPU internal RTC to restart the PMIC.

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