DESK-XZ7-L-AN-0001: Using a VirtualBox Ubuntu 20.04 Virtual Machine

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Applies to BORA Application Notes

Applies to BORA Xpress Application Notes

Applies to BORA Lite Application Notes

History
Issue Date	Notes
2024/01/30	DESK-XZ7-L-1.x.x release
2025/06/16	DESK-XZ7-L-2.x.x release

Virtual Machine[edit | edit source]

DESK-XZ7-L contains all the required software and documentation to start developing with Vivado, Vitis and Petalinux application on the BORA BORA Xpress BORA Lite platforms. DESK-XZ7-L provides also a virtual machine - a.k.a. DVDK - with the following features:

VirtualBox virtual machine (.OVA archive)
based on Lubuntu 20.04 LTS (64-bit version)
pre-installed VirtualBox Guest Additions
LXDE desktop environment
boot disk with the distro and pre-configured basic Linux services:
- TFTP: with base directory /tftpboot/
- NFS: configured through the /etc/exports file
pre-installed Vivado, Vitis and Petalinux requirements, as described here
- MVM has: 2 CPUs, 8192MB of RAM and 300 GB of HDD
administrator account (dvdk) with autologin. Please note that the user account credentials are provided with the development kit (you can find them in the README file contained in the sw/dvdk folder of the kit distribution)
- user: dvdk
- password: dvdk

Host setup[edit | edit source]

Since your OS, where VirtualBox is running, can be different compared to the version that we using, in case of an error we suggest updating VirtualBox to the latest release patch. For example, if we used virtualbox-6.1_6.1.18-142142 version of VirtualBox to test MVM but this does not work for you, update VirtualBox to the latest version of virtualbox-6.1_6.1.XX

As previously stated, host tools are based on a Managed Virtual Machine, we used virtualbox-6.1_6.1.18-142142 to perform virtual machine. MVM OVA files can be downloaded here. For accessing the DESK Reserved area please contact our helpdesk support channel

To install the Virtual Machine OVA file, please refer to this page.

It is worth remembering that accessing the git repositories is required to download target source code. For getting access, please refer to this page.

Virtual Machine updates[edit | edit source]

The Ubuntu distribution may ask for an update, if available, due to the Update Notifier.

The updates are not required for DESK Virtual Machine functionality.

It is suggested to not install the updates. They may change or corrupt what tested and documented in our wiki pages

If this is annoying for you, it is possible to disable it.

Installing Vivado and Vitis[edit | edit source]

Vivado and Vitis require a large amount of resources: we suggest using a build server instead of a Virtual Machine

For installing Vivado and Vitis, please follow the steps below:

download FPGAs_AdaptiveSoCs_Unified_2024.2_1113_1001_Lin64.bin from official Xilinx download page and copy the file in the MVM. The Xilinx-2024.2 directory has been created and the installation file has been copied. The version used in DESK-XZ7-L is Vivado ML 2024.2
change the file permission to executable

dvdk@vagrant:~$ mkdri -p Xilinx-2024.2 && cd Xilinx-2024.2
dvdk@vagrant:~/Xilinx-2024.2$ chmod u+x FPGAs_AdaptiveSoCs_Unified_2024.2_1113_1001_Lin64.bin

run FPGAs_AdaptiveSoCs_Unified_2024.2_1113_1001_Lin64.bin file

dvdk@vagrant:~/Xilinx-2024.2$ ./FPGAs_AdaptiveSoCs_Unified_2024.2_1113_1001_Lin64.bin 
Verifying archive integrity... All good.
Uncompressing AMD Installer for FPGAs and Adaptive SoCs.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
This is a fresh install.
INFO Could not detect the display scale (hDPI).
       If you are using a high resolution monitor, you can set the installer scale factor like this: 
       export XINSTALLER_SCALE=2
       setenv XINSTALLER_SCALE 2
INFO  - Started in: 4 Sec 
INFO  - Internet connection validated, can connect to internet. 
INFO  - Installing Edition: Vitis Unified Software Platform 
INFO  - Installation directory is /home/dvdk

Step for install Vivado and Vitis

The following screenshot refers to Vivado 2021.2 but can be used likewise for the Vivado 2024.2 installation

open Vivado from a terminal

dvdk@vagrant:~$ source Vivado/2024.2/settings64.sh 
dvdk@vagrant:~$ vivado

****** Vivado v2024.2 (64-bit)
  **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024
  **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
  **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
  **** Start of session at: Mon Jun 16 18:13:54 2025
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

start_gui

open Vitis from a terminal

dvdk@vagrant:~$ source Vitis/2024.2/settings64.sh 
dvdk@vagrant:~$ vitis

****** Vitis Development Environment
****** Vitis v2024.2 (64-bit)
  **** SW Build 5238363 on 2024-11-08-17:54:51
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

Example of building `bora.xsa` with Vivado[edit | edit source]

Here below there is an example of building bora.xsa using Vivado

dvdk@vagrant:~$ git clone --recursive git@gitlab.com:DAVEEmbeddedSystems/desk/desk-xz7-l/petalinux.git -b desk-xz7-l-2.0.0
Cloning into 'petalinux'...
The authenticity of host 'gitlab.com (172.65.251.78)' can't be established.
ECDSA key fingerprint is SHA256:HbW3g8zUjNSksFbqTiUWPWg2Bq1x8xdGUrliXFzSnUw.
Are you sure you want to continue connecting (yes/no/[fingerprint])? yes
Warning: Permanently added 'gitlab.com,172.65.251.78' (ECDSA) to the list of known hosts.
remote: Enumerating objects: 1297, done.
remote: Counting objects: 100% (70/70), done.
remote: Compressing objects: 100% (68/68), done.
remote: Total 1297 (delta 40), reused 0 (delta 0), pack-reused 1227 (from 1)
Receiving objects: 100% (1297/1297), 3.08 MiB | 5.36 MiB/s, done.
Resolving deltas: 100% (719/719), done.
Note: switching to '13055268986ea93853c7dfc2d70253a9ae0a266a'.

You are in 'detached HEAD' state. You can look around, make experimental
changes and commit them, and you can discard any commits you make in this
state without impacting any branches by switching back to a branch.

If you want to create a new branch to retain commits you create, you may
do so (now or later) by using -c with the switch command. Example:

  git switch -c <new-branch-name>

Or undo this operation with:

  git switch -

Turn off this advice by setting config variable advice.detachedHead to false

Submodule 'project-spec/meta-dave' (git@gitlab.com:DAVEEmbeddedSystems/desk/desk-xz7-l/meta-dave.git) registered for path 'project-spec/meta-dave'
Submodule 'vivado' (git@gitlab.com:DAVEEmbeddedSystems/desk/desk-xz7-l/vivado.git) registered for path 'vivado'
Cloning into '/home/dvdk/petalinux/project-spec/meta-dave'...
remote: Enumerating objects: 667, done.        
remote: Counting objects: 100% (87/87), done.        
remote: Compressing objects: 100% (74/74), done.        
remote: Total 667 (delta 45), reused 30 (delta 11), pack-reused 580 (from 1)        
Receiving objects: 100% (667/667), 28.85 MiB | 11.00 MiB/s, done.
Resolving deltas: 100% (303/303), done.
Cloning into '/home/dvdk/petalinux/vivado'...
remote: Enumerating objects: 761, done.        
remote: Counting objects: 100% (67/67), done.        
remote: Compressing objects: 100% (62/62), done.        
remote: Total 761 (delta 29), reused 0 (delta 0), pack-reused 694 (from 1)        
Receiving objects: 100% (761/761), 198.18 KiB | 1.37 MiB/s, done.
Resolving deltas: 100% (341/341), done.
Submodule path 'project-spec/meta-dave': checked out '988f0475300d2f5ff4cea89df5eebfb16e8ad28d'
Submodule path 'vivado': checked out '9ef273917ed988576a0f70c441a8afedfccccc82'
dvdk@vagrant:~$ cd petalinux/vivado/
dvdk@vagrant:~/petalinux/vivado$ source ~/Vivado/2024.2/settings64.sh
dvdk@vagrant:~/petalinux/vivado$ cp -r boards/ ~/Vivado/2024.2/data/.
dvdk@vagrant:~/petalinux/vivado$ vivado -mode tcl -source scripts/recreate_prj_bora_BASE.tcl -notrace -tclargs "gen_bitstream"

****** Vivado v2024.2 (64-bit)
  **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024
  **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
  **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
  **** Start of session at: Mon Jun 16 18:18:15 2025
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

source scripts/recreate_prj_bora_BASE.tcl -notrace
WARNING: [BD 41-2576] File '/home/dvdk/petalinux/vivado/bd/bora/ip/bora_processing_system7_0_0/bora_processing_system7_0_0.xci' referenced by design 'bora' could not be found.
INFO: [BD 41-434] Could not find an IP with XCI file by name: bora_processing_system7_0_0 
INFO: [BD 41-433] Design successfully migrated to use XCI files...
WARNING: [BD 41-2670] Found an incomplete address path from address space '/processing_system7_0/Data' to master interface '/processing_system7_0/M_AXI_GP0'. Please either complete or remove this path to resolve.
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_objects /processing_system7_0/Data'
Wrote  : </home/dvdk/petalinux/vivado/bd/bora/bora.bd> 
Verilog Output written to : /home/dvdk/petalinux/vivado/bd/bora/synth/bora.v
Verilog Output written to : /home/dvdk/petalinux/vivado/bd/bora/sim/bora.v
Verilog Output written to : /home/dvdk/petalinux/vivado/bd/bora/hdl/bora_wrapper.v
make_wrapper: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1479.375 ; gain = 103.695 ; free physical = 712 ; free virtual = 8262
INFO: Project created:bora
Generating BITSTREAM
INFO: [BD 41-1662] The design 'bora.bd' is already validated. Therefore parameter propagation will not be re-run.
Verilog Output written to : /home/dvdk/petalinux/vivado/bd/bora/synth/bora.v
Verilog Output written to : /home/dvdk/petalinux/vivado/bd/bora/sim/bora.v
Verilog Output written to : /home/dvdk/petalinux/vivado/bd/bora/hdl/bora_wrapper.v
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_GP0'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 .
Exporting to file /home/dvdk/petalinux/vivado/bd/bora/hw_handoff/bora.hwh
Generated Hardware Definition File /home/dvdk/petalinux/vivado/bd/bora/synth/bora.hwdef
generate_target: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1496.375 ; gain = 17.000 ; free physical = 660 ; free virtual = 8228
[Mon Jun 16 18:18:55 2025] Launched bora_processing_system7_0_0_synth_1, synth_1...
Run output will be captured here:
bora_processing_system7_0_0_synth_1: /home/dvdk/petalinux/vivado/vivado/bora.runs/bora_processing_system7_0_0_synth_1/runme.log
synth_1: /home/dvdk/petalinux/vivado/vivado/bora.runs/synth_1/runme.log
[Mon Jun 16 18:18:55 2025] Launched impl_1...
Run output will be captured here: /home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1512.387 ; gain = 16.012 ; free physical = 647 ; free virtual = 8224
[Mon Jun 16 18:18:55 2025] Waiting for impl_1 to finish...

*** Running vivado
    with args -log bora_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source bora_wrapper.tcl -notrace


****** Vivado v2024.2 (64-bit)
  **** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024
  **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
  **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
  **** Start of session at: Mon Jun 16 18:20:25 2025
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

source bora_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/dvdk/Vivado/2024.2/data/ip'.
Command: link_design -top bora_wrapper -part xc7z020clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Project 1-454] Reading design checkpoint '/home/dvdk/petalinux/vivado/bd/bora/ip/bora_processing_system7_0_0/bora_processing_system7_0_0.dcp' for cell 'bora_i/processing_system7_0'
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1547.594 ; gain = 0.000 ; free physical = 1182 ; free virtual = 7642
INFO: [Project 1-479] Netlist was created with Vivado 2024.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/dvdk/petalinux/vivado/bd/bora/ip/bora_processing_system7_0_0/bora_processing_system7_0_0.xdc] for cell 'bora_i/processing_system7_0/inst'
Finished Parsing XDC File [/home/dvdk/petalinux/vivado/bd/bora/ip/bora_processing_system7_0_0/bora_processing_system7_0_0.xdc] for cell 'bora_i/processing_system7_0/inst'
Parsing XDC File [/home/dvdk/petalinux/vivado/constr/bora_pinout.xdc]
WARNING: [Vivado 12-4702] SLEW is not a supported property on input port(s). Setting is ignored. [/home/dvdk/petalinux/vivado/constr/bora_pinout.xdc:7]
WARNING: [Vivado 12-4702] DRIVE is not a supported property on input port(s). Setting is ignored. [/home/dvdk/petalinux/vivado/constr/bora_pinout.xdc:8]
WARNING: [Vivado 12-4702] SLEW is not a supported property on input port(s). Setting is ignored. [/home/dvdk/petalinux/vivado/constr/bora_pinout.xdc:18]
WARNING: [Vivado 12-4702] DRIVE is not a supported property on input port(s). Setting is ignored. [/home/dvdk/petalinux/vivado/constr/bora_pinout.xdc:19]
Finished Parsing XDC File [/home/dvdk/petalinux/vivado/constr/bora_pinout.xdc]
Parsing XDC File [/home/dvdk/petalinux/vivado/constr/bora_timing.xdc]
Finished Parsing XDC File [/home/dvdk/petalinux/vivado/constr/bora_timing.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1719.125 ; gain = 0.000 ; free physical = 1074 ; free virtual = 7534
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

9 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 1813.281 ; gain = 94.156 ; free physical = 1002 ; free virtual = 7463

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 15e9f76d5

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2194.109 ; gain = 380.828 ; free physical = 595 ; free virtual = 7070

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 15e9f76d5

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 263 ; free virtual = 6738

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 15e9f76d5

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 263 ; free virtual = 6738
Phase 1 Initialization | Checksum: 15e9f76d5

Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 263 ; free virtual = 6738

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 15e9f76d5

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 263 ; free virtual = 6738

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 15e9f76d5

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 262 ; free virtual = 6738
Phase 2 Timer Update And Timing Data Collection | Checksum: 15e9f76d5

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 262 ; free virtual = 6737

Phase 3 Retarget
INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1af9dfaa7

Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 262 ; free virtual = 6737
Retarget | Checksum: 1af9dfaa7
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 24 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1af9dfaa7

Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 262 ; free virtual = 6737
Constant propagation | Checksum: 1af9dfaa7
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 262 ; free virtual = 6737
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 262 ; free virtual = 6737
Phase 5 Sweep | Checksum: 12a142f73

Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2534.008 ; gain = 0.000 ; free physical = 262 ; free virtual = 6737
Sweep | Checksum: 12a142f73
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 3 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 12a142f73

Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2566.023 ; gain = 32.016 ; free physical = 262 ; free virtual = 6737
BUFG optimization | Checksum: 12a142f73
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 12a142f73

Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2566.023 ; gain = 32.016 ; free physical = 262 ; free virtual = 6737
Shift Register Optimization | Checksum: 12a142f73
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 12a142f73

Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2566.023 ; gain = 32.016 ; free physical = 261 ; free virtual = 6737
Post Processing Netlist | Checksum: 12a142f73
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 16c563cf6

Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2566.023 ; gain = 32.016 ; free physical = 261 ; free virtual = 6737

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2566.023 ; gain = 0.000 ; free physical = 261 ; free virtual = 6737
Phase 9.2 Verifying Netlist Connectivity | Checksum: 16c563cf6

Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2566.023 ; gain = 32.016 ; free physical = 261 ; free virtual = 6737
Phase 9 Finalization | Checksum: 16c563cf6

Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2566.023 ; gain = 32.016 ; free physical = 261 ; free virtual = 6737
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |              24  |                                              1  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               3  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 16c563cf6

Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2566.023 ; gain = 32.016 ; free physical = 261 ; free virtual = 6737

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 16c563cf6

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2566.023 ; gain = 0.000 ; free physical = 261 ; free virtual = 6737

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 16c563cf6

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2566.023 ; gain = 0.000 ; free physical = 261 ; free virtual = 6737

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2566.023 ; gain = 0.000 ; free physical = 261 ; free virtual = 6737
Ending Netlist Obfuscation Task | Checksum: 16c563cf6

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2566.023 ; gain = 0.000 ; free physical = 261 ; free virtual = 6737
INFO: [Common 17-83] Releasing license: Implementation
31 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 2566.023 ; gain = 846.898 ; free physical = 261 ; free virtual = 6737
INFO: [Vivado 12-24828] Executing command : report_drc -file bora_wrapper_drc_opted.rpt -pb bora_wrapper_drc_opted.pb -rpx bora_wrapper_drc_opted.rpx
Command: report_drc -file bora_wrapper_drc_opted.rpt -pb bora_wrapper_drc_opted.pb -rpx bora_wrapper_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper_drc_opted.rpt.
report_drc completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.742 ; gain = 0.000 ; free physical = 216 ; free virtual = 6693
Wrote PlaceDB: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2596.742 ; gain = 0.000 ; free physical = 214 ; free virtual = 6691
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.742 ; gain = 0.000 ; free physical = 214 ; free virtual = 6691
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2596.742 ; gain = 0.000 ; free physical = 213 ; free virtual = 6689
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.742 ; gain = 0.000 ; free physical = 213 ; free virtual = 6689
Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2596.742 ; gain = 0.000 ; free physical = 212 ; free virtual = 6690
Write Physdb Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2596.742 ; gain = 0.000 ; free physical = 212 ; free virtual = 6690
INFO: [Common 17-1381] The checkpoint '/home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper_opt.dcp' has been generated.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2642.336 ; gain = 0.000 ; free physical = 173 ; free virtual = 6650
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 106c7561d

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2642.336 ; gain = 0.000 ; free physical = 173 ; free virtual = 6650
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2642.336 ; gain = 0.000 ; free physical = 173 ; free virtual = 6651

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 16aa73bad

Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2642.336 ; gain = 0.000 ; free physical = 167 ; free virtual = 6649

Phase 1.3 Build Placer Netlist Model
WARNING: [Place 30-2953] Timing driven mode will be turned off because no critical terminals were found.
Phase 1.3 Build Placer Netlist Model | Checksum: 1a5a64d9e

Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2666.348 ; gain = 24.012 ; free physical = 165 ; free virtual = 6648

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1a5a64d9e

Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2666.348 ; gain = 24.012 ; free physical = 164 ; free virtual = 6648
Phase 1 Placer Initialization | Checksum: 1a5a64d9e

Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2666.348 ; gain = 24.012 ; free physical = 164 ; free virtual = 6648

Phase 2 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2666.348 ; gain = 0.000 ; free physical = 164 ; free virtual = 6648

Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2666.348 ; gain = 24.012 ; free physical = 164 ; free virtual = 6648
INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
Ending Placer Task | Checksum: 16aa73bad

Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2666.348 ; gain = 24.012 ; free physical = 164 ; free virtual = 6648
48 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
Running report generation with 2 threads.
INFO: [Vivado 12-24828] Executing command : report_utilization -file bora_wrapper_utilization_placed.rpt -pb bora_wrapper_utilization_placed.pb
INFO: [Vivado 12-24828] Executing command : report_io -file bora_wrapper_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2666.348 ; gain = 0.000 ; free physical = 153 ; free virtual = 6638
INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file bora_wrapper_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2666.348 ; gain = 0.000 ; free physical = 157 ; free virtual = 6641
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2666.348 ; gain = 0.000 ; free physical = 157 ; free virtual = 6641
Wrote PlaceDB: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00 . Memory (MB): peak = 2666.348 ; gain = 0.000 ; free physical = 156 ; free virtual = 6641
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2666.348 ; gain = 0.000 ; free physical = 156 ; free virtual = 6641
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00 . Memory (MB): peak = 2666.348 ; gain = 0.000 ; free physical = 156 ; free virtual = 6641
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2666.348 ; gain = 0.000 ; free physical = 156 ; free virtual = 6641
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2666.348 ; gain = 0.000 ; free physical = 155 ; free virtual = 6642
Write Physdb Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00 . Memory (MB): peak = 2666.348 ; gain = 0.000 ; free physical = 155 ; free virtual = 6642
INFO: [Common 17-1381] The checkpoint '/home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper_placed.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: b1aff12d ConstDB: 0 ShapeSum: a2fdd790 RouteDB: 15f972f0
INFO: [Timing 38-35] Done setting XDC timing constraints.
Post Restoration Checksum: NetGraph: d47c7f7c | NumContArr: b9c35630 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 31391cae6

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2771.824 ; gain = 105.477 ; free physical = 128 ; free virtual = 6522

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 31391cae6

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2771.824 ; gain = 105.477 ; free physical = 128 ; free virtual = 6522

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 31391cae6

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2771.824 ; gain = 105.477 ; free physical = 128 ; free virtual = 6522
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 29e8cfeec

Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 2791.559 ; gain = 125.211 ; free physical = 122 ; free virtual = 6502

Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 134
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 134
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 2 Router Initialization | Checksum: 29e8cfeec

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Phase 3 Global Routing
Phase 3 Global Routing | Checksum: 29e8cfeec

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Phase 4 Initial Routing

Phase 4.1 Initial Net Routing Pass
 Number of Nodes with overlaps = 0
Phase 4.1 Initial Net Routing Pass | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6495
Phase 4 Initial Routing | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6495

Phase 5 Rip-up And Reroute

Phase 5.1 Global Iteration 0
Phase 5.1 Global Iteration 0 | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494
Phase 5 Rip-up And Reroute | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Phase 6 Delay and Skew Optimization

Phase 6.1 Delay CleanUp
Phase 6.1 Delay CleanUp | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Phase 6.2 Clock Skew Optimization
Phase 6.2 Clock Skew Optimization | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494
Phase 6 Delay and Skew Optimization | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Phase 7 Post Hold Fix

Phase 7.1 Hold Fix Iter
Phase 7.1 Hold Fix Iter | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494
Phase 7 Post Hold Fix | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Phase 8 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0156881 %
  Global Horizontal Routing Utilization  = 0.0187627 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 8 Route finalize | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Phase 9 Verifying routed nets

 Verification completed successfully
Phase 9 Verifying routed nets | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Phase 10 Depositing Routes
Phase 10 Depositing Routes | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Phase 11 Post Process Routing
Phase 11 Post Process Routing | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Phase 12 Post Router Timing
Phase 12 Post Router Timing | Checksum: 248eaf47f

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494
Total Elapsed time in route_design: 27.28 secs

Phase 13 Post-Route Event Processing
Phase 13 Post-Route Event Processing | Checksum: 204b1db82

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494
INFO: [Route 35-16] Router Completed Successfully
Ending Routing Task | Checksum: 204b1db82

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
59 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 2797.840 ; gain = 131.492 ; free physical = 114 ; free virtual = 6494
INFO: [Vivado 12-24828] Executing command : report_drc -file bora_wrapper_drc_routed.rpt -pb bora_wrapper_drc_routed.pb -rpx bora_wrapper_drc_routed.rpx
Command: report_drc -file bora_wrapper_drc_routed.rpt -pb bora_wrapper_drc_routed.pb -rpx bora_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper_drc_routed.rpt.
report_drc completed successfully
INFO: [Vivado 12-24828] Executing command : report_methodology -file bora_wrapper_methodology_drc_routed.rpt -pb bora_wrapper_methodology_drc_routed.pb -rpx bora_wrapper_methodology_drc_routed.rpx
Command: report_methodology -file bora_wrapper_methodology_drc_routed.rpt -pb bora_wrapper_methodology_drc_routed.pb -rpx bora_wrapper_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 4 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -file bora_wrapper_timing_summary_routed.rpt -pb bora_wrapper_timing_summary_routed.pb -rpx bora_wrapper_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
Running report generation with 2 threads.
INFO: [Vivado 12-24828] Executing command : report_route_status -file bora_wrapper_route_status.rpt -pb bora_wrapper_route_status.pb
INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file bora_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file bora_wrapper_bus_skew_routed.rpt -pb bora_wrapper_bus_skew_routed.pb -rpx bora_wrapper_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
INFO: [Vivado 12-24828] Executing command : report_power -file bora_wrapper_power_routed.rpt -pb bora_wrapper_power_summary_routed.pb -rpx bora_wrapper_power_routed.rpx
Command: report_power -file bora_wrapper_power_routed.rpt -pb bora_wrapper_power_summary_routed.pb -rpx bora_wrapper_power_routed.rpx
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
79 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file bora_wrapper_clock_utilization_routed.rpt
generate_parallel_reports: Time (s): cpu = 00:00:16 ; elapsed = 00:00:07 . Memory (MB): peak = 2898.613 ; gain = 100.773 ; free physical = 132 ; free virtual = 6442
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2898.613 ; gain = 0.000 ; free physical = 132 ; free virtual = 6442
Wrote PlaceDB: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00 . Memory (MB): peak = 2898.613 ; gain = 0.000 ; free physical = 132 ; free virtual = 6442
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2898.613 ; gain = 0.000 ; free physical = 132 ; free virtual = 6442
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2898.613 ; gain = 0.000 ; free physical = 130 ; free virtual = 6441
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2898.613 ; gain = 0.000 ; free physical = 130 ; free virtual = 6441
Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2898.613 ; gain = 0.000 ; free physical = 129 ; free virtual = 6441
Write Physdb Complete: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2898.613 ; gain = 0.000 ; free physical = 129 ; free virtual = 6441
INFO: [Common 17-1381] The checkpoint '/home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper_routed.dcp' has been generated.
Command: write_bitstream -force bora_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./bora_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
91 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:12 . Memory (MB): peak = 3273.047 ; gain = 374.434 ; free physical = 138 ; free virtual = 6049
INFO: [Common 17-206] Exiting Vivado at Mon Jun 16 18:21:37 2025...
[Mon Jun 16 18:21:42 2025] impl_1 finished
wait_on_runs: Time (s): cpu = 00:01:28 ; elapsed = 00:02:47 . Memory (MB): peak = 1512.387 ; gain = 0.000 ; free physical = 2327 ; free virtual = 8238
Command: write_cfgmem -format BIN -size 16 -interface SMAPx32 -disablebitswap -loadbit {up 0x0 /home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper.bit} /home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper.bin
Creating config memory files...
INFO: [Writecfgmem 68-23] Start address provided has been multiplied by a factor of 4 due to the use of interface SMAPX32.
Creating bitstream load up from address 0x00000000
Loading bitfile /home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper.bit
Writing file /home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper.bin
Writing log file /home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper.prm
===================================
Configuration Memory information
===================================
File Format        BIN
Interface          SMAPX32
Size               16M
Start Address      0x00000000
End Address        0x00FFFFFF

Addr1         Addr2         Date                    File(s)
0x00000000    0x003DBAFB    Jun 16 18:21:37 2025    /home/dvdk/petalinux/vivado/vivado/bora.runs/impl_1/bora_wrapper.bit
6 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_cfgmem completed successfully
Write BITSTREAM Done!!!!
INFO: [Project 1-1918] Creating Hardware Platform: /home/dvdk/petalinux/vivado/vivado/bora.xsa ...
WARNING: [Project 1-645] Board images not set in Hardware Platform.
INFO: [Project 1-1943] The Hardware Platform can be used for Hardware
INFO: [Project 1-1941] Successfully created Hardware Platform: /home/dvdk/petalinux/vivado/vivado/bora.xsa
INFO: [Hsi 55-2053] elapsed time for repository (/home/dvdk/Vivado/2024.2/data/embeddedsw) loading 0 seconds
DONE!
INFO: [Common 17-206] Exiting Vivado at Mon Jun 16 18:21:47 2025...
dvdk@vagrant:~/petalinux/vivado$ ls -l vivado/
total 360
drwxrwxr-x 4 dvdk dvdk   4096 Jun 16 18:18 bora.cache
drwxrwxr-x 2 dvdk dvdk   4096 Jun 16 18:18 bora.hw
drwxrwxr-x 2 dvdk dvdk   4096 Jun 16 18:18 bora.ip_user_files
drwxrwxr-x 6 dvdk dvdk   4096 Jun 16 18:18 bora.runs
drwxrwxr-x 3 dvdk dvdk   4096 Jun 16 18:18 bora.srcs
-rw-rw-r-- 1 dvdk dvdk  15240 Jun 16 18:21 bora.xpr
-rw-rw-r-- 1 dvdk dvdk 331442 Jun 16 18:21 bora.xsa
dvdk@vagrant:~/petalinux/vivado$

Installing Petalinux[edit | edit source]

Petalinux building in the MVM requires large amount of resources: it is strongly suggested to use a build server

For installing Petalinux, please follow the steps here below

download petalinux-v2024.2-11062026-installer.run from official Xilinx download page and copy the file in the MVM. The Xilinx-2021.2 directory has been created for this purposes. The version used in DESK-XZ7-L-1.0.1 is Petalinux 2024.2

change the file permission and run it

dvdk@vagrant:~$ chmod u+x Xilinx-2024.2/petalinux-v2024.2-11062026-installer.run

create the Petalinux directory

dvdk@vagrant:~$ mkdir Petalinux && cd Petalinux

run petalinux-v2024.2-11062026-installer.run file

dvdk@vagrant:~/Petalinux$ ../Xilinx-2024.2/petalinux-v2024.2-11062026-installer.run 
PetaLinux CMD tools installer version 2024.2
============================================
[INFO] Checking free disk space
[INFO] Checking installed tools
[INFO] Checking installed development libraries
[INFO] Checking network and other services

LICENSE AGREEMENTS

PetaLinux SDK contains software from a number of sources.  Please review
the following licenses and indicate your acceptance of each to continue.

You do not have to accept the licenses, however if you do not then you may 
not use PetaLinux SDK.

Use PgUp/PgDn to navigate the license viewer, and press 'q' to close

Press Enter to display the license agreements
Do you accept Xilinx End User License Agreement? [y/N] > y
Do you accept Third Party End User License Agreement? [y/N] > y
Enter target directory for SDK (default: /home/dvdk/Petalinux): /home/dvdk/Petalinux
[WARNING] PetaLinux installation directory: /home/dvdk/Petalinux is not empty!
[WARNING] If you continue, existing files will be overwritten! Proceed [y/N]? y
[INFO] Installing PetaLinux SDK...done
[INFO] Setting it up...done
[INFO] Extracting xsct tarball...done
[INFO] PetaLinux SDK has been successfully set up and is ready to be used.
dvdk@vagrant:~/Petalinux$

Example of building `wic` image with Petalinux[edit | edit source]

Here below there is an example of build an wic image, with Petalinux using the result of previously reported Vivado example

dvdk@vagrant:~/petalinux$ source ../Petalinux/settings.sh 
*************************************************************************************************************************************************
The PetaLinux source code and images provided/generated are for demonstration purposes only.
Please refer to https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2741928025/Moving+from+PetaLinux+to+Production+Deployment
 for more details
*************************************************************************************************************************************************
PetaLinux environment set to '/home/dvdk/Petalinux'
WARNING: /bin/sh is not bash! 
bash is PetaLinux recommended shell. Please set your default shell to bash.
[INFO] Checking free disk space
[INFO] Checking installed tools
[INFO] Checking installed development libraries
[INFO] Checking network and other services
dvdk@vagrant:~/petalinux$ cp project-spec/configs/config_bora project-spec/configs/config
dvdk@vagrant:~/petalinux$ petalinux-config --get-hw-description vivado/vivado/bora.xsa --silentconfig
[INFO] Getting hardware description
[INFO] Renaming bora.xsa to system.xsa
[INFO] Extracting yocto SDK to components/yocto. This may take time!
[INFO] Bitbake is not available, some functionality may be reduced.
[INFO] Using HW file: /home/dvdk/petalinux/project-spec/hw-description/system.xsa
[INFO] Getting Platform info from HW file
[INFO] Generating Kconfig for project
[INFO] Silentconfig project
[INFO] Generating kconfig for rootfs
[INFO] Silentconfig rootfs
[INFO] Generating configuration files
[INFO] Adding user layers
[INFO] Generating machine conf file
[INFO] Generating plnxtool conf file
[INFO] Generating workspace directory
NOTE: Starting bitbake server...
NOTE: Started PRServer with DBfile: /home/dvdk/petalinux/build/cache/prserv.sqlite3, Address: 127.0.0.1:37603, PID: 5426
INFO: Specified workspace already set up, leaving as-is
INFO: Enabling workspace layer in bblayers.conf
[INFO] Successfully configured project
dvdk@vagrant:~/petalinux$ petalinux-build
[INFO] Building project
[INFO] Bitbake is not available, some functionality may be reduced.
[INFO] Using HW file: /home/dvdk/petalinux/project-spec/hw-description/system.xsa
[INFO] Getting Platform info from HW file
[INFO] Silentconfig project
[INFO] Silentconfig rootfs
[INFO] Generating configuration files
[INFO] Generating workspace directory
NOTE: Starting bitbake server...
NOTE: Started PRServer with DBfile: /home/dvdk/petalinux/build/cache/prserv.sqlite3, Address: 127.0.0.1:36533, PID: 2344
INFO: Specified workspace already set up, leaving as-is
[INFO] bitbake petalinux-image-minimal
NOTE: Started PRServer with DBfile: /home/dvdk/petalinux/build/cache/prserv.sqlite3, Address: 127.0.0.1:46729, PID: 2408
WARNING: XSCT has been deprecated. It will still be available for several releases. In the future, it's recommended to start new projects with SDT workflow.
Loading cache: 100% |#########################################################################################################################################################| Time: 0:00:22
Loaded 8465 entries from dependency cache.
Parsing recipes: 100% |#######################################################################################################################################################| Time: 0:00:02
Parsing of 5814 .bb files complete (5811 cached, 3 parsed). 8468 targets, 1106 skipped, 27 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Checking sstate mirror object availability: 100% |############################################################################################################################| Time: 0:02:13
Sstate summary: Wanted 2310 Local 141 Mirrors 0 Missed 2169 Current 2019 (6% match, 49% complete)
NOTE: Executing Tasks
WARNING: fetchmail-6.4.38-r0 do_package_qa: QA Issue: File /usr/bin/fetchmail in package fetchmail contains reference to TMPDIR [buildpaths]
WARNING: canutils-4.0.6-r0 do_fetch: Failed to fetch URL git://git.pengutronix.de/git/tools/canutils.git;protocol=git;branch=master, attempting MIRRORS if available
NOTE: Tasks Summary: Attempted 9279 tasks of which 4878 didn't need to be rerun and all succeeded.

Summary: There were 3 WARNING messages.
[INFO] Successfully copied built images to tftp dir: /tftpboot
[INFO] Successfully built project
dvdk@vagrant:~/petalinux$ petalinux-package boot --u-boot --force
[INFO] File in BOOT BIN: "/home/dvdk/petalinux/images/linux/zynq_fsbl.elf"
[INFO] File in BOOT BIN: "/home/dvdk/petalinux/images/linux/u-boot.elf"
[INFO] File in BOOT BIN: "/home/dvdk/petalinux/images/linux/system.dtb"
[INFO] Generating zynq binary package BOOT.BIN...
[INFO] 

****** Bootgen v2024.2
  **** Build date : Oct 21 2024-10:58:34
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.


[INFO]   : Bootimage generated successfully


[INFO] Binary is ready.
[INFO] Successfully Generated BIN File
dvdk@vagrant:~/petalinux$ petalinux-package wic --bootfiles "BOOT.BIN boot.scr image.ub"
[INFO] Sourcing build environment
[INFO] bitbake wic-tools
NOTE: Started PRServer with DBfile: /home/dvdk/petalinux/build/cache/prserv.sqlite3, Address: 127.0.0.1:35369, PID: 2463
WARNING: XSCT has been deprecated. It will still be available for several releases. In the future, it's recommended to start new projects with SDT workflow.
Loading cache: 100% |#########################################################################################################################################################| Time: 0:00:22
Loaded 8465 entries from dependency cache.
Parsing recipes: 100% |#######################################################################################################################################################| Time: 0:00:02
Parsing of 5814 .bb files complete (5811 cached, 3 parsed). 8468 targets, 1106 skipped, 27 masked, 0 errors.
NOTE: Resolving any missing task queue dependencies
Sstate summary: Wanted 78 Local 0 Mirrors 0 Missed 78 Current 330 (0% match, 80% complete)####################################################################                | ETA:  0:00:00
Initialising tasks: 100% |####################################################################################################################################################| Time: 0:00:07
NOTE: Executing Tasks
NOTE: Tasks Summary: Attempted 1024 tasks of which 826 didn't need to be rerun and all succeeded.

Summary: There was 1 WARNING message.
[INFO] Extracting rootfs, This may take time!
[INFO] Creating wic image
[INFO] wic create /home/dvdk/petalinux/build/rootfs.wks --rootfs-dir /home/dvdk/petalinux/build/wic/rootfs --bootimg-dir /home/dvdk/petalinux/images/linux --kernel-dir /home/dvdk/petalinux/images/linux --outdir  /home/dvdk/petalinux/build/wic/wic-tmp -n /home/dvdk/petalinux/build/tmp/work/cortexa9t2hf-neon-xilinx-linux-gnueabi/wic-tools/1.0/recipe-sysroot-native 
INFO: Creating image(s)...

WARNING: bootloader config not specified, using defaults

INFO: The new image(s) can be found here:
  /home/dvdk/petalinux/build/wic/wic-tmp/rootfs-202506180731-sda.direct

The following build artifacts were used to create the image(s):
  ROOTFS_DIR:                   /home/dvdk/petalinux/build/wic/rootfs
  BOOTIMG_DIR:                  /home/dvdk/petalinux/images/linux
  KERNEL_DIR:                   /home/dvdk/petalinux/images/linux
  NATIVE_SYSROOT:               /home/dvdk/petalinux/build/tmp/work/cortexa9t2hf-neon-xilinx-linux-gnueabi/wic-tools/1.0/recipe-sysroot-native

INFO: The image(s) were created using OE kickstart file:
  /home/dvdk/petalinux/build/rootfs.wks
[INFO] Successfully Generated image: /home/dvdk/petalinux/images/linux/petalinux-sdimage.wic
dvdk@vagrant:~/petalinux$ ls -la images/linux/
total 2529268
drwxr-xr-x 3 dvdk dvdk       4096 Jun 18 09:32 .
drwxr-xr-x 3 dvdk dvdk       4096 Jun 17 15:21 ..
-rw-rw-r-- 1 dvdk dvdk    1175704 Jun 18 09:15 BOOT.BIN
-rw-rw-r-- 1 dvdk dvdk        189 Jun 18 09:15 bootgen.bif
-rw-r--r-- 1 dvdk dvdk       3830 Jun 17 18:39 boot.scr
-rw-r--r-- 1 dvdk dvdk       8401 Jun 17 16:36 config
-rw-r--r-- 1 dvdk dvdk    6250683 Jun 17 19:25 image.ub
-rw-rw-r-- 1 dvdk dvdk 6442455040 Jun 18 09:32 petalinux-sdimage.wic
drwxr-xr-x 2 dvdk dvdk       4096 Jun 17 18:39 pxelinux.cfg
-rw-r--r-- 1 dvdk dvdk  441798656 Jun 17 20:25 rootfs.cpio
-rw-r--r-- 1 dvdk dvdk  185766541 Jun 17 20:26 rootfs.cpio.gz
-rw-r--r-- 1 dvdk dvdk  185766605 Jun 17 20:26 rootfs.cpio.gz.u-boot
-rw-r--r-- 1 dvdk dvdk  734792704 Jun 17 20:26 rootfs.ext4
-rw-r--r-- 1 dvdk dvdk  233046016 Jun 17 20:26 rootfs.jffs2
-rw-r--r-- 1 dvdk dvdk      48495 Jun 17 20:22 rootfs.manifest
-rw-r--r-- 1 dvdk dvdk       1945 Jun 17 20:23 rootfs.qemuboot.conf
-rw-r--r-- 1 dvdk dvdk    2680366 Jun 17 20:23 rootfs.spdx.tar.zst
-rw-r--r-- 1 dvdk dvdk  186857845 Jun 17 20:26 rootfs.tar.gz
-rw-r--r-- 1 dvdk dvdk    1630613 Jun 17 20:22 rootfs.testdata.json
-rw-r--r-- 1 dvdk dvdk    4045672 Jun 17 09:02 system.bit
-rw-r--r-- 1 dvdk dvdk      20567 Jun 17 15:21 system.dtb
-rwxr-xr-x 1 dvdk dvdk    1050872 Jun 17 17:02 u-boot.bin
-rw-r--r-- 1 dvdk dvdk    1071439 Jun 17 17:02 u-boot-dtb.bin
-rw-r--r-- 1 dvdk dvdk    1075960 Jun 17 17:02 u-boot-dtb.elf
-rwxr-xr-x 1 dvdk dvdk    8522624 Jun 17 17:02 u-boot.elf
-rw-r--r-- 1 dvdk dvdk    6228256 Jun 17 19:25 uImage
-rw-r--r-- 1 dvdk dvdk   19127920 Jun 17 19:25 vmlinux
-rw-r--r-- 1 dvdk dvdk    6228192 Jun 17 19:25 zImage
-rw-r--r-- 1 dvdk dvdk     412204 Jun 17 15:41 zynq_fsbl.elf
dvdk@vagrant:~/petalinux$

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DESK-XZ7-L-AN-0001: Using a VirtualBox Ubuntu 20.04 Virtual Machine

Contents

Virtual Machine[edit | edit source]

Host setup[edit | edit source]

Virtual Machine updates[edit | edit source]

Installing Vivado and Vitis[edit | edit source]

Example of building `bora.xsa` with Vivado[edit | edit source]

Installing Petalinux[edit | edit source]

Example of building `wic` image with Petalinux[edit | edit source]

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DESK-XZ7-L-AN-0001: Using a VirtualBox Ubuntu 20.04 Virtual Machine

Contents

Virtual Machine[edit | edit source]

Host setup[edit | edit source]

Virtual Machine updates[edit | edit source]

Installing Vivado and Vitis[edit | edit source]

Example of building bora.xsa with Vivado[edit | edit source]

Installing Petalinux[edit | edit source]

Example of building wic image with Petalinux[edit | edit source]

Navigation menu

Search

Example of building `bora.xsa` with Vivado[edit | edit source]

Example of building `wic` image with Petalinux[edit | edit source]