Watchdog (Bora)

Info Box Applies to Bora

An external watchdog (Maxim MAX6373) is connected to the PORSTn signal. During normal operation, the microprocessor should repeatedly toggle the watchdog input WDI before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset the μP. By default WDI is connected to Zynq's PS_MIO15_500 I/O. WDI is available on Bora connectors as EX_WDT_REARM. EX_WDT_REARM is pulled-down through a 22kOhm resistor.

On request, PS_MIO15_500 can be disconnected from WDI (please contact Sales Department for more details). This configuration provides two independent signals (EX_WDT_REAM and PS_MIO15_500) that allow the implementation of customized solutions on carrier board. For example you may want to use the Zynq's System Watchdog Timer (SWDT) instead of MAX6373 to reset the system through PS_MIO15_500 that can be configured as SWDT reset.

The MAX6373 watchdog timer is pin-selectable and the timer can be configured through the WD_SET0 (J2.100), WD_SET1 (J2.98) and WD_SET2 (J2.96) signals. As a default, the watchdog is configured through a pull-up/pull-down resistors network (WD_SET[2..0] = 110) that keeps the watchdog timer inactive at startup. Startup delay ends when WDI sees its first level transition. The default watchdog timeout period is 10 s.

The configuration can be changed by optional external circuitry implemented on the carrier board.