User contributions
10 February 2015
Power (AxelUltra)
Power rails and related signals
m+13
Power (AxelUltra)
Power rails and related signals
m+331
Power (AxelLite)
Power rails and related signals
m+330
9 February 2015
5 February 2015
Integration guide (Bora/BoraX/BoraLite)
How to implement workaround suggested by Xilinx on BoraEVB
m+79
Integration guide (Bora/BoraX/BoraLite)
How to implement workaround suggested by Xilinx on BoraEVB
m+2
Integration guide (Bora/BoraX/BoraLite)
How to implement workaround suggested by Xilinx on BoraEVB
m+4
Integration guide (Bora/BoraX/BoraLite)
PS' I²C buses
m+894
Integration guide (Bora/BoraX/BoraLite)
PS' I²C buses
m+6
Integration guide (Bora/BoraX/BoraLite)
PS' I²C buses
+1,534
File:Bora-i2c-glitch-filter.png
no edit summary
4 February 2015
2 February 2015
Bora Embedded Linux Kit (BELK)
BELK software components
m+100
Axel Embedded Linux Kit (XELK)
XELK software components
m+6
Axel Embedded Linux Kit (XELK)
XELK software components
m+512
Bora Embedded Linux Kit (BELK)
BELK software components
m+8
Software Manual (Diva)
DIVELK software components
m-9
Diva Embedded Linux Kit (DIVELK)
DIVELK software components
m-9
29 January 2015
Programmable logic (Bora)
FPGA Bank 13 (Zynq 7020 only)
m+48
Programmable logic (Bora)
Introduction
m+47
Pinout (Bora)
J3 even pins (2 to 140)
m-16
Pinout (Bora)
J3 odd pins (1 to 139)
m-24
Pinout (Bora)
J3 odd pins (1 to 139)
m+684
Pinout (Bora)
no edit summary
m+741
Programmable logic (Bora)
Introduction
m+18
Programmable logic (Bora)
FPGA Bank 13 (Zynq 7020 only)
m+13
Programmable logic (Bora)
FPGA Bank 13 (Zynq 7020 only)
m+219
Programmable logic (Bora)
Introduction
m+151
Pinout (Bora)
J3 odd pins (1 to 139)
m+144
Pinout (Bora)
J3 even pins (2 to 140)
m+398
Pinout (Bora)
J3 odd pins (1 to 139)
m+453
28 January 2015
BoraEVB
Known limitations
m+433
AxelEVB-Lite
Known limitations
m+451
Axel Embedded Linux Kit (XELK)
Known Limitations
m+5
Axel Embedded Linux Kit (XELK)
Known Limitations
m+327
Bora Embedded Linux Kit (BELK)
Known Limitations
m+2
Bora Embedded Linux Kit (BELK)
Known Limitations
m-4
Bora Embedded Linux Kit (BELK)
Known Limitations
+8
Bora Embedded Linux Kit (BELK)
Known Limitations
m+308
Processing system peripherals (Bora)
Gigabit Ethernet
m+118
Pinout (Bora)
J2 odd pins (1 to 139)
m+76
27 January 2015
Pinout (Bora)
J2 odd pins (1 to 139)
m+2
Pinout (Bora)
J2 odd pins (1 to 139)
m+102
Pinout (Bora)
J2 even pins (2 to 140)
m+245
20 January 2015
14 January 2015
15 December 2014
Power (Bora/BoraLite)
no edit summary
m+263
Pinout (Bora)
J2 odd pins (1 to 139)
m+46
Carrier board design guidelines (SOM)
PCI Express
m+771