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Programmable logic (Bora)

47 bytes added, 11:21, 29 January 2015
m
Introduction
|User defined<br>VIO=FPGA_VDDIO_BANK13<br>'''1.8 to 3.3V'''
|J3.95<br>J3.96<br>J3.97<br>J3.98<br>J3.99
|Bank 13 is available only with Zynq XC7Z020 part number. Although this bank is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway , either to ground or to an external I/O voltage.
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