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Carrier board design guidelines (SOM)

771 bytes added, 09:40, 15 December 2014
m
PCI Express
* * Including SoM trace length
* Preferred underneath plane over entire trace length GND.
 
=== LVDS ===
 
==== PCB ====
 
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|'''Parameter for LVDS Differential Pairs'''
| align="center" style="background:#f0f0f0;"|'''Min'''
| align="center" style="background:#f0f0f0;"|'''Typ'''
| align="center" style="background:#f0f0f0;"|'''Max'''
|-
| Differential Impedance [Ohm]||85||100||115
|-
| Common Mode Impedance [Ohm]||46.75||55||63.25
|-
| Gap than other signals (reccomended)||-||2xgap||-
|-
| Intra pair skew [mils]*||-||-||5
|-
| Inter pair skew [mils]**||-||400||-
|-
| Maximum allowed stub||-||-||0
|-
|}
 
* Prefer to route traces on TOP layer, referring them to a continuos GND plane.
* * Not includes SOM's length.
* ** Typical value can be relaxed depending on LVDS clock frequency
=== LCD Interface ===

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