Difference between revisions of "BORA Lite SOM/BORA Lite Hardware/Peripherals/EEPROM"
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Latest revision as of 15:58, 8 January 2024
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| History | |||
|---|---|---|---|
| Issue Date | Notes | ||
| First version | |||
| 2023/07/18 | Minor changes | ||
An on-board Microchip 24AA32AT device provides an added storage device for factory settings:
- the first 32 bytes of the device are RESERVED: this region stores the bytes for the ConfigID on BORA Lite SOMs configured for booting from NAND device (without NOR SPI on board)
- the device is write protected using the EEPROM_WP
The device has some configuration pins:
- three address pins for configuring the I2C adddress A0, A1, A2 internally configured as A[0..2]='000'
- the EEPROM_WP is connected to J2.9 pin on the JTAG connector and should not be externally connected
