BELK-TN-007: FreeRTOS on single-core Bora Lite SoM

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Revision as of 11:28, 5 February 2020 by U0001 (talk | contribs) (Testbed)

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Info Box
Bora5-small.jpg Applies to Bora
BORA Xpress.png Applies to BORA Xpress
BORALite-TOP.png Applies to BORA Lite


Warning-icon.png This technical note was validated against specific versions of hardware and software. What is described here may not work with other versions. Warning-icon.png

History[edit | edit source]

Version Date Notes
1.0.0 February 2020 First public release

Introduction[edit | edit source]

In general, Bora Lite SoM is suited for compact, cost-sensitive applications for which Bora or BoraX would be overkilling. In this scenario, Bora Lite is often equipped with XC7Z007 or XC7Z014 SoC's, which implement single-core processors. In combination with FreeRTOS, such configurations can be the right solution to address applications with real-time constraints as well. This Technical Note (TN) shows how to use FreeRTOS on a single-core Bora Lite model. TBD

Testbed[edit | edit source]

From the hardware perspective, the testbed is like the one shown here. It consists of a BoraXEVB carrier board, a Bora Lite Adapter, and a single-core Bora Lite SoM.

The BoraXEVB carrier board is set up to make the SoM boot from the microSD card.

As bootloader, the U-Boot release provided by the BELK kit is used:

U-Boot SPL 2017.01-belk-4.1.1 (Jan 08 2020 - 16:46:11)
mmc boot
Trying to boot from MMC1
reading fpga.bit
spl_load_image_fat: error reading image fpga.bit, err - -1
spl: error reading image fpga.bit, err - 1
reading u-boot.img
reading u-boot.img


U-Boot 2017.01-belk-4.1.1 (Jan 08 2020 - 16:46:11 +0100), Build: belk-4.1.1

Model: Bora
Board: Xilinx Zynq
I2C:   ready
DRAM:  ECC disabled 1 GiB
Relocating to 3ff14000, new gd at 3ead3ee8, sp at 3ead3ec0
NAND:  1024 MiB
MMC:   sdhci@e0100000: 0 (SD)
reading bora.env
In:    serial@e0001000
Out:   serial@e0001000
Err:   serial@e0001000
Model: Bora
Board: Xilinx Zynq
SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 32 MiB
SOM ConfigID CRC mismatch for 0xff0101ff (was 0xffffffff, expected 0xca9a6d16) at block 2 (offset 96): using default
SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 32 MiB
SOM UniqueID not found, using default
SOM ConfigID#: ffffffff
SOM UniqueID#: ffffffff:ffffffff
ds2431_readmem(): error in chip reset
ds2431_readmem(): error in reading buffer
ds2431_readmem(): error in chip reset
ds2431_readmem(): error in reading buffer
CB ConfigID CRC mismatch for 0x00000000 (was 0x00000000, expected 0x2144df1c) at block 3 (offset 96): using default
CB ConfigID#: ffffffff
CB UniqueID#: 00000000:00000000
Net:   ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id
eth0: ethernet@e000b000
Bora>

The procedure described in this TN makes use of the Xilinx SDK (XSDK) too. Specifically, the version 2019.1 running on a Windows PC was used.

Setting up the Hello, world! project[edit | edit source]

This section illustrates how to set up the software project. As an example, the classical Hello, world!-type appliation was used.

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Running the application[edit | edit source]

Hello from Freertos example main
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World
Rx task received string from Tx task: Hello World