BELK-TN-003: Video processing and hardware/software partitioning

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Bora5-small.jpg Applies to Bora
BORA Xpress.png Applies to BORA Xpress

History[edit | edit source]

Version Date Notes
1.0.0 June 2016 First public release

Introduction[edit | edit source]

This white paper describes a video processing system - built upon Bora/BoraEVB - that satisfies specific functional and safety requirements.

From the functional point of view, it is required to (FR denotes a functional requirement):

  • [FR1] acquire two independent video streams
  • [FR2] mix the input stream and visualize them on a HDMI monitor
  • [FR3] visualize informational and statistical data on a 7" LVDS TFT LCD.

Safety requirements (SR for short) are:

  • [SR1] FR1 and FR2 must be enabled as quickly as possible upon power-up
  • [SR2] once started, video processing chain must keep operating even if software running on PS hangs.

The implementation combines different techniques that are available on Zynq platform to implement a hardware/software partitioning that allows to meet system requirements.

Implementation[edit | edit source]

The following picture shows a simplified block diagram of the entire system [1].

Simplified block diagram

At top level, the natural PS/PL partitioning has been exploited: the video processing chain is entirely implemented in the PL, while PS domain is used for initializing, supervising and informational data visualization. The following section describes in more detail the actual implementation.

[1] At the time of this writing not all of the shown modules have been completed.

PL subsystem[edit | edit source]

PL subsystem integrates several functional modules. The video processing chain is described first, as it represents the most important part of it.

Video processing chain supports two video sources as per requirement FR1:

  • OV7670 camera module (640x480 @ 30fps)
  • generic 1280x720 @ 60fps stream over HDMI connection.

Each video source is connected to a specific interface module:

  • std res video i/f
    • converts BT656-encoded LVTTL bus into AXI4 stream
    • performs color space conversion (YUV 4:2:2 to 24-bit RGB)
  • hi res video i/f
    • converts TMDS differential signals to AXI4 stream.

Video frames encapsulated in AXI4 streams are then stored - by AXI-VDMAs not shown in the picture - in two independent buffers, both implemented on SDRAM bank #1 (this 16-bit wide bank refers to U14 component of BoraXEVB board). Frames are then retrieved by AXI-VDMAs from these buffers and are forwarded to On-Screen Display LogiCORE IP block (named video mixer in the diagram) that mixes them. The resulting stream in processed by LCD controller #1 module that converts it to TMDS signals feeding the external monitor.

The latency gauge module is used to perform video latency measurement. Specifically, it is used to measure the time it takes a frame to traverse the entire video chain, from the input to the output interface.

To satisfy requirement FR3, a second controller (LCD controller #0 in the diagram) is instantiated, feeding a 7" LVDS LCD. LVDS signals are generated by the FPGA directly.

PS subsystem[edit | edit source]

At software level, partitioning has been implemented by using the well-known AMP technique combined with SafeG monitor (for more details please see this white paper). FreeRTOS domain - associated to core #1 - is the first to come up and takes care of video processing chain initialization. Linux domain - associated to core #0 - controls LCD controller #0 to visualize informational data on 7" LCD. It also provides generic connectivity such as TCP/IP networking over Ethernet connection.

TrustZone technology - enabled with the help of SafeG monitor - allows to enforce the partitioning by preventing software running in Linux domain to access video processing chain resources.

The combination of

  • short FreeRTOS domain boot time
  • quick PL programming performed by FSBL

allows to minimize the video processing enabling time upon power-on (requirement SR1).

Notes about SDRAM banks organization[edit | edit source]

The block diagram shows two distinct SDRAM banks. Bank #0 is 32-bit wide and includes memory regions used by FreeRTOS and by Linux. It is also used to implement the frame buffer associated to 7" LCD screen. Bank #1 is 16-bit wide and it is used to implement frame buffer for HDMI screen only. Bank #0 is accessed via Zynq's native DDR memory controller. Bank #1 is accessed via memory controller instantiated in PL and created by Interface Generator (MIG).

SDRAM banks physical separation allows to satisfy requirement SR2: even if native DDR memory controller stops working [1], video processing chain is unaffected because it relies on its own frame buffer.

[1] For example because a misconfiguration caused by a software bug in Linux drivers or by malicious code injected by an attacker.

Video latency and SDRAM arbitering[edit | edit source]

Apart from requirement SR2, the availability of two independent SDRAM banks provides an advantage in terms of performances too.

unico banco di ram per riduzione costi ma più fragile

Future work[edit | edit source]

References[edit | edit source]