BELK-TN-003: Video processing and hardware/software partitioning

From DAVE Developer's Wiki
Revision as of 16:17, 16 June 2016 by U0001 (talk | contribs) (Introduction)

Jump to: navigation, search
Info Box
Bora5-small.jpg Applies to Bora
BORA Xpress.png Applies to BORA Xpress

History[edit | edit source]

Version Date Notes
1.0.0 June 2016 First public release

Introduction[edit | edit source]

This white paper describes a video processing system - built upon Bora/BoraEVB - that satisfies specific functional and safety requirements.

From the functional point of view, it is required to (FR denotes a functional requirement):

  • [FR1] acquire two independent video streams
  • [FR2] mix the input stream and visualize them on a HDMI monitor
  • [FR3] visualize informational and statistical data on a 7" LVDS TFT LCD.

Safety requirements (SR for short) are:

  • [SR1]FR1 and FR2 must be enabled as quickly as possible upon power-up
  • [SR2] once started, video processing chain must keep operating even if software running on PS hangs.

The implementation combines different techniques that are available on Zynq platform to implement a hardware/software partitioning that allows to meet system requirements.

Implementation[edit | edit source]

The following picture shows a simplified block diagram of the entire system [1].

Concept block diagram of the system without monitoring subsystem

At top level, the natural PS/PL partitioning has been exploited: the video processing chain is entirely implemented in the PL, while PS domain is used for initializing, supervisioning and informational data visualization. The following section describes in more detail the actual implementation.

[1] At the time of this writing not all of the shown modules have been completed.

PL subsystem[edit | edit source]

Video sources consist of:

  • OV7670 camera module (640x480 @ 30fps)
  • generic 1280x720 @ 60fps stream over HDMI connection.

PL implements the following modules:

  • interfaces to video sources
    • OV7670 camera module: this module converts BT656-encoded LVTTL bus into AXI4 stream; it

unico banco di ram per riduzione costi ma più fragile

PS subsystem[edit | edit source]

(for more details see also this white paper)

References[edit | edit source]