BELK-AN-006: Enabling dual Gigabit Ethernet support on BoraEVB/BoraXEVB

Info Box Applies to Bora

History

Version	Date	BELK version	Notes
1.0.0		2.2.0	First release

Introduction

Thanks to the migration to linux kernel 3.10.17, BELK 2.2.0 allows to cleanly support dual Gigabit Ethernet configuration on BoraEVB. This application note describes how to implement such configuration, providing a reference design for Vivado 2014.4.

Block diagram and Vivado design

Simplified block diagram of dual Ethernet congifuration is shown in the following picture.

TBD

First Ethernet port refers to J8 connector of BoraEVB carrier board and is based on Zynq's Gigabit Ethernet Controller 0 (Gem0). This controller is mapped at physical address 0xE000B000. Second Ethernet port refers to J9 connector of BoraEVB carrier board and is based on Zynq's Gigabit Ethernet Controller 1 (Gem1). This controller is mapped at physical address 0xE000C000.

The fundamental difference between the two interfaces is the PHY interfacing. In case of Gem0, PHY is mounted on Bora SoM and it is interfaced directly to Processor Subsystem (PS) via MIO pads. In case of Gem1 instead, PHY is populated on BoraEVB (U9) and it is interfaced to Programmable Logic (PL) pads. Thus it is necessary to enable EMIO routing and to instantiate a GMII to RGMII bridge in PL as per PHY's interface requirement. Please note that RGMII signals belong to bank #34. Since this bank is powered at 3.3V (High Range I/O mode), RGMII duty cycle distortion specification is not matched. In case of carrier board designed for production environments, it is recommended to use a lower voltage levels - and thus a different PL bank - as described on section I/O Standard and Placement of PG160 GMII to RGMII LogiCORE IP Product Guide.

The following picture shows the block diagram of the Vivado project:

To implement frame buffer, a portion of main SDRAM is used. This area is allocated at runtime by linux frame buffer driver.

Every pixel on the display has 2 possible states, ON (light pixel) or OFF (dark pixel). In the frame buffer, each pixel is represented by 8 bits. A byte of value 0xFF represents an ON pixel, and all the other values (0xFE down to 0x00) represent an OFF pixel.

At this link the Vivado design is available for download. Please note that, even if this application note is based on BELK 2.2.0, this design has been implemented with Vivado 2013.4.

Two PL IOs, controlled by the linux driver, manage the power supplies of the display (5V and 12V from BoraEVB to Lumineq Display).

Enabling dual Ethernet configuration in linux kernel

To enable frame buffer driver user need to:

• get the pre-built binaries from this link.

Kernel and device tree can also be built with the following procedure:

• update Bora kernel repository (as described here)
• checkout bora-feat-lcd-support branch (using git checkout bora-feat-lcd-support command)
• build the updated kernel source as usual

Put the binaries on the first (FAT32) partition of your BELK 2.2.0 SD card, overwriting the original one if needed. Please note that you need the following files:

• boot.bin
• bora.dtb
• uImage
• fpga.bin
• uEnv.txt

Insert the SD card into BoraEVB and turn on the board.

During kernel bootstrap, the following messages are printed out on console, indicating framebuffer driver has been loaded succesfully:

[    0.600553] borafb_lum borafb_lum.0: fb0: Virtual frame buffer device, using 16384K of video memory @ phys 2d900000

You will also see two Tuxes on the top left corner of the LCD, indicating that this Linux system has two cores: