Difference between revisions of "AXEL ULite SOM/AXEL ULite Hardware/Power and Reset/Reset scheme and control signals"

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<section begin="History" />
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{{AppliesToAXELULite}}
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
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|-
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |New documentation layout
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|7028|2017/08/04}}
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Add PMIC_PWRON information
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2020/10/15
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Minor changes
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<section end="History" />
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__FORCETOC__
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<section begin="Body" />
  
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==Introduction==
 
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Reset scheme is strictly related to power supply unit. As such, reading of [[Power_(AXELULite)|this page]] is strongly recommended.
 
  
 
== Reset scheme and control signals ==
 
== Reset scheme and control signals ==
 +
Reset scheme is strictly related to power supply unit. As such, reading of [[Power (AXEL ULite)|this page]] is strongly recommended.
  
 
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
 
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
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Some signals that are related to reset circuitry are pulled-up to VDD_SNVS_IN. This voltage is generated by PMIC PF3000's VSNVS LDO/Switch and its actual value depends on:
 
Some signals that are related to reset circuitry are pulled-up to VDD_SNVS_IN. This voltage is generated by PMIC PF3000's VSNVS LDO/Switch and its actual value depends on:
 
* voltage applied to PF3000 VIN pin
 
* voltage applied to PF3000 VIN pin
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** in case of AXELULite this pin is connected to VIN_SOM power rail
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** in case of AXEL ULite this pin is connected to VIN_SOM power rail
 
* voltage applied to PF3000 LICELL pin
 
* voltage applied to PF3000 LICELL pin
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** in case of AXELULite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL).
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** in case of AXEL ULite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL).
 
Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''.
 
Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''.
  
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=== Handling CPU-initiated software reset ===
 
=== Handling CPU-initiated software reset ===
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By default, iMX6UL processor does not assert any external signal when it initiates a software reset sequence. This might not guarantee a safe system reset in all conditions. For these reasons, AXELULite integrates a specific circuit that, in combination with the use on iMX6UL watchdog timer (WDT), guarantees a full hardware reset in case a software reset is issued. It is worth remembering that when this reset is triggered, a full power up cycle is issued. This technique makes use of the GPIO1_IO08 pin. Particular attention needs to be paid in case this pin needs to be used at carrier board level as well. For more details please contact the [mailto:support-axel@dave.eu technical support].
+
By default, iMX6UL processor does not assert any external signal when it initiates a software reset sequence. This might not guarantee a safe system reset in all conditions. For these reasons, AXEL ULite integrates a specific circuit that, in combination with the use on iMX6UL watchdog timer (WDT), guarantees a full hardware reset in case a software reset is issued. It is worth remembering that when this reset is triggered, a full power up cycle is issued. This technique makes use of the GPIO1_IO08 pin. Particular attention needs to be paid in case this pin needs to be used at carrier board level as well. For more details please contact the [mailto:support-axel@dave.eu technical support].
  
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This technique is supported by [[AXELULite_and_SBC_Lynx_Embedded_Linux_Kit_(XUELK)|AXELULite Embedded LinuxKit]].
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This technique is supported by [[AXEL ULite and SBC Lynx Embedded Linux Kit (XUELK)|AXEL ULite Embedded LinuxKit]].
  
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==References==
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==== Forcing a software reset using an external signal ====
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As described before, GPIO1_IO08 is used by internal watchdog for triggering a software reset using [[Pinout_(AXEL_ULite)#PMIC_PWRON|PMIC_PWRON]].
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The same input signal, can be used with an external push-button for triggering a software reset too.
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[[Pinout_(AXEL_ULite)#PMIC_PWRON|PMIC_PWRON]] has an internal pull-up (see [[Reset_scheme_(AXEL_ULite)#Reset_scheme_and_control_signals|Reset scheme]]) and must be driven with an open-drain signal
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===References===
 
{{reflist}}
 
{{reflist}}
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<section end="Body" />

Latest revision as of 10:11, 9 January 2024

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History
Issue Date Notes

2016/07/21

New documentation layout

2017/08/04

Add PMIC_PWRON information
2020/10/15 Minor changes



Reset scheme and control signals[edit | edit source]

Reset scheme is strictly related to power supply unit. As such, reading of this page is strongly recommended.

The following picture shows the simplified block diagram of reset scheme and voltage monitoring.

Simplified block diagram of reset circuitry and voltage monitoring

VDD_SNVS_IN[edit | edit source]

Some signals that are related to reset circuitry are pulled-up to VDD_SNVS_IN. This voltage is generated by PMIC PF3000's VSNVS LDO/Switch and its actual value depends on:

  • voltage applied to PF3000 VIN pin
    • in case of AXEL ULite this pin is connected to VIN_SOM power rail
  • voltage applied to PF3000 LICELL pin
    • in case of AXEL ULite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL).

Hence it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.

For more details please refer to section VSNVS LDO/Switch of Freescale Semiconductor PF3000 Advance Information document[1].

CPU_PORn[edit | edit source]

The following devices can assert this active-low signal:

  • PMIC
  • voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition.

Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.

Handling CPU-initiated software reset[edit | edit source]

By default, iMX6UL processor does not assert any external signal when it initiates a software reset sequence. This might not guarantee a safe system reset in all conditions. For these reasons, AXEL ULite integrates a specific circuit that, in combination with the use on iMX6UL watchdog timer (WDT), guarantees a full hardware reset in case a software reset is issued. It is worth remembering that when this reset is triggered, a full power up cycle is issued. This technique makes use of the GPIO1_IO08 pin. Particular attention needs to be paid in case this pin needs to be used at carrier board level as well. For more details please contact the technical support.

This technique is supported by AXEL ULite Embedded LinuxKit.

Forcing a software reset using an external signal[edit | edit source]

As described before, GPIO1_IO08 is used by internal watchdog for triggering a software reset using PMIC_PWRON. The same input signal, can be used with an external push-button for triggering a software reset too.

PMIC_PWRON has an internal pull-up (see Reset scheme) and must be driven with an open-drain signal

References[edit | edit source]

  1. ↑ Freescale Semiconductor, PF3000 Advance Information - Power Management Integrated Circuit (PMIC) for i.MX 7 & i.MX 6SL/SX/UL


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