AXEL ULite SOM/AXEL ULite Hardware/Power and Reset/Reset scheme and control signals
| HOME | SOMs | SBCs | ToloMEO Embedded Assistant |  GET A QUOTE
|
 ONLINE HELPDESK
|
| Roadmap | IoT Services | ML/AI services | Embedded Design Services |
| History | |||
|---|---|---|---|
| Issue Date | Notes | ||
| New documentation layout | |||
| Add PMIC_PWRON information | |||
| 2020/10/15 | Minor changes | ||
Contents
Reset scheme and control signals[edit | edit source]
Reset scheme is strictly related to power supply unit. As such, reading of this page is strongly recommended.
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
VDD_SNVS_IN[edit | edit source]
Some signals that are related to reset circuitry are pulled-up to VDD_SNVS_IN. This voltage is generated by PMIC PF3000's VSNVS LDO/Switch and its actual value depends on:
- voltage applied to PF3000 VIN pin
- in case of AXEL ULite this pin is connected to VIN_SOM power rail
- voltage applied to PF3000 LICELL pin
- in case of AXEL ULite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL).
Hence it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.
For more details please refer to section VSNVS LDO/Switch of Freescale Semiconductor PF3000 Advance Information document[1].
CPU_PORn[edit | edit source]
The following devices can assert this active-low signal:
- PMIC
- voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition.
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
Handling CPU-initiated software reset[edit | edit source]
By default, iMX6UL processor does not assert any external signal when it initiates a software reset sequence. This might not guarantee a safe system reset in all conditions. For these reasons, AXEL ULite integrates a specific circuit that, in combination with the use on iMX6UL watchdog timer (WDT), guarantees a full hardware reset in case a software reset is issued. It is worth remembering that when this reset is triggered, a full power up cycle is issued. This technique makes use of the GPIO1_IO08 pin. Particular attention needs to be paid in case this pin needs to be used at carrier board level as well. For more details please contact the technical support.
This technique is supported by AXEL ULite Embedded LinuxKit.
Forcing a software reset using an external signal[edit | edit source]
As described before, GPIO1_IO08 is used by internal watchdog for triggering a software reset using PMIC_PWRON. The same input signal, can be used with an external push-button for triggering a software reset too.
PMIC_PWRON has an internal pull-up (see Reset scheme) and must be driven with an open-drain signal
References[edit | edit source]
- ↑ Freescale Semiconductor, PF3000 Advance Information - Power Management Integrated Circuit (PMIC) for i.MX 7 & i.MX 6SL/SX/UL
