Difference between revisions of "AXEL Lite SOM/AXEL Lite Hardware/Peripherals/PCI Express"
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==Peripheral PCI Express == | ==Peripheral PCI Express == | ||
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=== Description === | === Description === | ||
| − | The PCI Express interface available on AXEL Lite is based on | + | The PCI Express interface available on AXEL Lite is based on i.MX6 SoC and supports the following standards and features: |
| − | + | * PCI Express Base Specification, Revision 2.0 (including legacy 2.5-Gbps support) @ 5.0 Gbps data rate | |
| + | * PCI Express Base Specification, Revision 1.1 @ 2.5Gbps data rate | ||
| − | * | + | ==== PHY features ==== |
| − | * | + | * 5 Gbps data transmission rate |
| − | * | + | * Integrated PHY includes transmitter, receiver and PLL |
| − | * | + | * Programmable RX equalization |
| + | * 5Gb/s PCIe Gen 2 and 2.5Gb/s PCIe Gen 1.1 test modes | ||
===Pin mapping=== | ===Pin mapping=== | ||
Revision as of 14:40, 7 October 2020
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Peripheral PCI Express[edit | edit source]
Description[edit | edit source]
The PCI Express interface available on AXEL Lite is based on i.MX6 SoC and supports the following standards and features:
- PCI Express Base Specification, Revision 2.0 (including legacy 2.5-Gbps support) @ 5.0 Gbps data rate
- PCI Express Base Specification, Revision 1.1 @ 2.5Gbps data rate
PHY features[edit | edit source]
- 5 Gbps data transmission rate
- Integrated PHY includes transmitter, receiver and PLL
- Programmable RX equalization
- 5Gb/s PCIe Gen 2 and 2.5Gb/s PCIe Gen 1.1 test modes
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
