AXEL Lite SOM/AXEL Lite Hardware/Peripherals/PCI Express
| History | |||
|---|---|---|---|
| Version | Issue Date | Notes | |
| 1.0.0 | Oct 2020 | New documentation layout | |
Peripheral PCI Express[edit | edit source]
Description[edit | edit source]
The PCI Express interface available on AXEL Lite is based on i.MX6 SoC and supports the following standards and features:
- PCI Express Base Specification, Revision 2.0 (including legacy 2.5-Gbps support) @ 5.0 Gbps data rate
- PCI Express Base Specification, Revision 1.1 @ 2.5Gbps data rate
PHY features[edit | edit source]
- 5 Gbps data transmission rate
- Integrated PHY includes transmitter, receiver and PLL
- Programmable RX equalization
- 5Gb/s PCIe Gen 2 and 2.5Gb/s PCIe Gen 1.1 test modes
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
