Difference between revisions of "AXEL Lite SOM/AXEL Lite Hardware/Peripherals/I2C"

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==Peripheral I2C ==
 
==Peripheral I2C ==
  
''TBD: sostituire le sezioni con le informazioni sull'uso della periferica''
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The Inter IC (I2C) provides functionality of a standard I2C slave and master. The I2C is designed to be compatible with the standard NXP I2C bus protocol.
''Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMI''
 
  
 
=== Description  ===
 
=== Description  ===
  
The MIPI interface available on AXEL Lite is based on xxxxx ''TBD:SOC name'' SoC.  
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The I2C interfaces available on AXEL Lite is based on i.Mx6 SoC.  
  
The MIPI port supports the following standards and features:
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The I2C ports support the following standards and features:
  
* High-Definition Multimedia Interface Specification, Version 1.4a
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* Multimaster operation
* Support for up to 1080p at 60Hz HDTV display resolutions and up to QXGA graphic display resolutions.
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* Software programmability for one of 64 different serial clock frequencies
* Support for 4k x 2k and 3D video formats
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* Software-selectable acknowledge bit
* Support for up to 16-bit Deep Color modes
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* Interrupt-driven, byte-by-byte data transfer
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* Arbitration-lost interrupt with automatic mode switching from master to slave
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* Start and stop signal generation/detection
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* Repeated Start signal generation
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* Acknowledge bit generation/detection
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* Bus-busy detection
  
 
===Pin mapping===
 
===Pin mapping===

Revision as of 17:00, 7 October 2020

History
Version Issue Date Notes
1.0.0 Oct 2020 New documentation layout


Peripheral I2C[edit | edit source]

The Inter IC (I2C) provides functionality of a standard I2C slave and master. The I2C is designed to be compatible with the standard NXP I2C bus protocol.

Description[edit | edit source]

The I2C interfaces available on AXEL Lite is based on i.Mx6 SoC.

The I2C ports support the following standards and features:

  • Multimaster operation
  • Software programmability for one of 64 different serial clock frequencies
  • Software-selectable acknowledge bit
  • Interrupt-driven, byte-by-byte data transfer
  • Arbitration-lost interrupt with automatic mode switching from master to slave
  • Start and stop signal generation/detection
  • Repeated Start signal generation
  • Acknowledge bit generation/detection
  • Bus-busy detection

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section