Difference between revisions of "AURA SOM/Part number composition"

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{| style="border-collapse:collapse; "
 
{| style="border-collapse:collapse; "
 
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
|-  
 
|-  
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
 
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
|-
 
|-
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |x.x.x
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | {{oldid|17886|2023/05/17}}
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | Mon YEAR
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | Preliminary information
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | description
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|-
 +
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | {{oldid|18662|2023/08/31}}
 +
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | Official release
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|-
 +
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" | 2024/02/09
 +
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" | Added more details about P/N structure.
 
|}
 
|}
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<section end=History/>
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<section end="History" />__FORCETOC__<section begin="Body" />
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__FORCETOC__
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−
<section begin=Body/>
 
  
 
==Part number composition==
 
==Part number composition==
−
AURA SOM module part number is identified by the following digit-code table:
+
AURA SOM module part number is composed by several fields as follows.
−
{|class="wikitable" style="width:50%"
+
 
−
!style="width:10%"|Part number structure
+
[Family][SOC][RAM][Storage][Boot Mode][RFU][RFU][Temperature range][PCB revision][Manufacturing option][Software Configuration]
−
!style="width:40%"|Options
+
 
−
!style="width:20%"|Description
+
Each field is detailed in the following table.
 +
{| class="wikitable" style="width:53%" "
 +
! style="width:10%" |Part number structure
 +
! style="width:50%" |Options
 +
! style="width:20%" |Description
 
|-
 
|-
 
!Family
 
!Family
−
| '''xxx'''
+
| '''DAU'''
 
| Family prefix code
 
| Family prefix code
 
|-
 
|-
−
!XXX
+
!SOC
 
|
 
|
−
* XXX
+
{|
 +
|A: PIMX9352CVUXMAA
 +
|1.7GHz
 +
|Dual Core
 +
|Tj: (-40+105)
 +
|Full Feature
 +
(Preliminary samples)
 +
|-
 +
|B: MIMX9352DVVxMAB
 +
|1.7GHz
 +
|Dual Core
 +
|Tj: (0+95)
 +
|Full Feature
 +
|-
 +
|C: MIMX9352CVVxMAB
 +
|1.7GHz
 +
|Dual Core
 +
|Tj: (-40+105)
 +
|Full Feature
 +
|-
 +
|D: MIMX9352XVVxMAB
 +
|1.7GHz
 +
|Dual Core
 +
|Tj: (-40+125)
 +
|Full Feature
 +
|-
 +
|E: MIMX9351DVVxMAB
 +
|1.7GHz
 +
|Single Core
 +
|Tj: (0+95)
 +
|Full Feature
 +
|-
 +
|F: MIMX9351CVVxMAB
 +
|1.7GHz
 +
|Single Core
 +
|Tj: (-40+105)
 +
|Full Feature
 +
|-
 +
|G: MIMX9351XVVxMAB
 +
|1.7GHz
 +
|Single Core
 +
|Tj: (-40+125)
 +
|Full Feature
 +
|-
 +
|H: MIMX9332DVVxMAB
 +
|1.7GHz
 +
|Dual Core
 +
|Tj: (0+95)
 +
|No NPU
 +
|-
 +
|I: MIMX9332CVVxMAB
 +
|1.7GHz
 +
|Dual Core
 +
|Tj: (-40+105)
 +
|No NPU
 +
|-
 +
|J: MIMX9332XVVxMAB
 +
|1.7GHz
 +
|Dual Core
 +
|Tj: (-40+125)
 +
|No NPU
 +
|-
 +
|K: MIMX9331DVVxMAB
 +
|1.7GHz
 +
|Single Core
 +
|Tj: (0+95)
 +
|No NPU
 +
|-
 +
|L: MIMX9331CVVxMAB
 +
|1.7GHz
 +
|Single Core
 +
|Tj: (-40+105)
 +
|No NPU
 +
|-
 +
|M: MIMX9331XVVxMAB
 +
|1.7GHz
 +
|Single Core
 +
|Tj: (-40+125)
 +
|No NPU
 +
|-
 +
|N: MIMX9302DVVxDAB
 +
|900 MHz
 +
|Dual Core
 +
|Tj: (0+95)
 +
|Reduced Features
 +
|-
 +
|O: MIMX9302CVVxDAB
 +
|900 MHz
 +
|Dual Core
 +
|Tj: (-40+105)
 +
|Reduced Features
 +
|-
 +
|P: MIMX9301DVVxDAB
 +
|900 MHz
 +
|Single Core
 +
|Tj: (0+95)
 +
|Reduced Features
 +
|-
 +
|Q: MIMX9301CVVxDAB
 +
|900 MHz
 +
|Single Core
 +
|Tj: (-40+105)
 +
|Reduced Features
 +
|}
 
*
 
*
−
|These options depends on XXX. Other versions can be available, please contact [https://www.dave.eu/helpdesk technical support]
+
|These options depends on NXP P/N description [https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-93-applications-processor-family-arm-cortex-a55-ml-acceleration-power-efficient-mpu:i.MX93?tab=Buy_Parametric_Tab#/ available here]. Other versions can be available, please contact [https://www.dave.eu/helpdesk technical support]
 
|-
 
|-
−
!XXX
+
!RAM
 +
|
 +
* 1: 1GB LPDDR4
 +
* 2: 2GB LPDDR4
 
|
 
|
−
* XXX
 
−
*
 
−
|XXX
 
 
|-
 
|-
 +
!Storage
 +
eMMC/NAND/QSPI
 +
|
 +
* 0: No Storage on board
 +
* 1: 16MB NOR SPI, 8GB eMMC
 +
* 2: 256MB NAND, 8GB eMMC
 +
* 3: 8GB eMMC, no NAND/NOR (SD3 available)
 +
* 4: 256MB NAND, no eMMC (SD1 available)
 +
* 5: 4GB eMMC, no NAND/NOR (SD3 available)
 +
* 6: 16MB NOR SPI, 4GB eMMC
 +
|SPI NOR and NAND are alternatives mounting options
 +
|-
 +
!Boot Mode:
 +
|
 +
* 0: on board SPI NOR
 +
* 1: on board eMMC
 +
* 2: on board SPI NAND
 +
|The boot modes listed here are "single boot", meaning that the Cortex-A55 is the first core to boot.
 +
 +
Other options are available on-demand, however. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact [mailto:sales@dave.eu sales@dave.eu].
 +
|-
 +
!RFU
 +
|
 +
* 0: RFU
 +
|
 +
|-
 +
!RFU
 +
|
 +
* 0: RFU
 +
|
 
|-
 
|-
 
!Temperature range
 
!Temperature range
Line 43: Line 183:
 
* C - Commercial grade: suitable for 0-70°C envirronment
 
* C - Commercial grade: suitable for 0-70°C envirronment
 
* I - Industrial grade: suitable for 40 - 85°C envirronment
 
* I - Industrial grade: suitable for 40 - 85°C envirronment
−
* XXX
 
 
|
 
|
 
|-
 
|-
Line 49: Line 188:
 
|
 
|
 
* 0: first version
 
* 0: first version
−
* 1: XXX
 
−
*
 
 
|PCB release may change for manufacturing purposes (i.e. text fixture adaptation)
 
|PCB release may change for manufacturing purposes (i.e. text fixture adaptation)
 
|-
 
|-
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|
 
|
 
* R: RoHS compliant
 
* R: RoHS compliant
−
*
 
 
|typically connected to production process and quality
 
|typically connected to production process and quality
 
|-
 
|-
 
!Software Configuration
 
!Software Configuration
 
| -00: standard factory u-boot pre-programmed
 
| -00: standard factory u-boot pre-programmed
−
-XX: custom version
 
 
|If customers require custom SW deployed this section should be defined and agreed. Please contact [https://www.dave.eu/helpdesk technical support]
 
|If customers require custom SW deployed this section should be defined and agreed. Please contact [https://www.dave.eu/helpdesk technical support]
 
|}
 
|}
  
 
=== Example ===
 
=== Example ===
−
AURA SOM code '''XXXXXXXXXXX-00'''
+
AURA SOM code '''DAUB13100I0R-00'''
  
−
* XXX - xxxxx
+
* B MIMX9352DVVxMAB 1.7GHz Dual Core Tj: (0+95) Full Feature
−
* X - xxxxx
+
* 1 - 1GB LPDDR4
−
* X - xxxxx
+
* 3 - 8GB eMMC
−
* -XX - xxxxx
+
* 1 - eMMC boot
 +
* 0 - RFU
 +
* 0 - RFU
 +
* I - Industrial grade: -40 to +85°C
 +
* 0 - first version
 +
* R - RoHS compliant
 +
* -00 -  
 
----
 
----
  
 
[[Category:AURA]]
 
[[Category:AURA]]

Latest revision as of 14:36, 12 February 2024

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History
Issue Date Notes

2023/05/17

Preliminary information

2023/08/31

Official release
2024/02/09 Added more details about P/N structure.


Part number composition[edit | edit source]

AURA SOM module part number is composed by several fields as follows.

[Family][SOC][RAM][Storage][Boot Mode][RFU][RFU][Temperature range][PCB revision][Manufacturing option][Software Configuration]

Each field is detailed in the following table.

Part number structure Options Description
Family DAU Family prefix code
SOC
A: PIMX9352CVUXMAA 1.7GHz Dual Core Tj: (-40+105) Full Feature

(Preliminary samples)

B: MIMX9352DVVxMAB 1.7GHz Dual Core Tj: (0+95) Full Feature
C: MIMX9352CVVxMAB 1.7GHz Dual Core Tj: (-40+105) Full Feature
D: MIMX9352XVVxMAB 1.7GHz Dual Core Tj: (-40+125) Full Feature
E: MIMX9351DVVxMAB 1.7GHz Single Core Tj: (0+95) Full Feature
F: MIMX9351CVVxMAB 1.7GHz Single Core Tj: (-40+105) Full Feature
G: MIMX9351XVVxMAB 1.7GHz Single Core Tj: (-40+125) Full Feature
H: MIMX9332DVVxMAB 1.7GHz Dual Core Tj: (0+95) No NPU
I: MIMX9332CVVxMAB 1.7GHz Dual Core Tj: (-40+105) No NPU
J: MIMX9332XVVxMAB 1.7GHz Dual Core Tj: (-40+125) No NPU
K: MIMX9331DVVxMAB 1.7GHz Single Core Tj: (0+95) No NPU
L: MIMX9331CVVxMAB 1.7GHz Single Core Tj: (-40+105) No NPU
M: MIMX9331XVVxMAB 1.7GHz Single Core Tj: (-40+125) No NPU
N: MIMX9302DVVxDAB 900 MHz Dual Core Tj: (0+95) Reduced Features
O: MIMX9302CVVxDAB 900 MHz Dual Core Tj: (-40+105) Reduced Features
P: MIMX9301DVVxDAB 900 MHz Single Core Tj: (0+95) Reduced Features
Q: MIMX9301CVVxDAB 900 MHz Single Core Tj: (-40+105) Reduced Features
These options depends on NXP P/N description available here. Other versions can be available, please contact technical support
RAM
  • 1: 1GB LPDDR4
  • 2: 2GB LPDDR4
Storage

eMMC/NAND/QSPI

  • 0: No Storage on board
  • 1: 16MB NOR SPI, 8GB eMMC
  • 2: 256MB NAND, 8GB eMMC
  • 3: 8GB eMMC, no NAND/NOR (SD3 available)
  • 4: 256MB NAND, no eMMC (SD1 available)
  • 5: 4GB eMMC, no NAND/NOR (SD3 available)
  • 6: 16MB NOR SPI, 4GB eMMC
 SPI NOR and NAND are alternatives mounting options
Boot Mode:
  • 0: on board SPI NOR
  • 1: on board eMMC
  • 2: on board SPI NAND
 The boot modes listed here are "single boot", meaning that the Cortex-A55 is the first core to boot.

Other options are available on-demand, however. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact sales@dave.eu.

RFU
  • 0: RFU
RFU
  • 0: RFU
Temperature range
  • C - Commercial grade: suitable for 0-70°C envirronment
  • I - Industrial grade: suitable for 40 - 85°C envirronment
PCB revision
  • 0: first version
 PCB release may change for manufacturing purposes (i.e. text fixture adaptation)
Manufacturing option
  • R: RoHS compliant
 typically connected to production process and quality
Software Configuration -00: standard factory u-boot pre-programmed If customers require custom SW deployed this section should be defined and agreed. Please contact technical support

Example[edit | edit source]

AURA SOM code DAUB13100I0R-00

  • B MIMX9352DVVxMAB 1.7GHz Dual Core Tj: (0+95) Full Feature
  • 1 - 1GB LPDDR4
  • 3 - 8GB eMMC
  • 1 - eMMC boot
  • 0 - RFU
  • 0 - RFU
  • I - Industrial grade: -40 to +85°C
  • 0 - first version
  • R - RoHS compliant
  • -00 -
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