AURA SOM/AURA Hardware/Power and Reset/Reset scheme and control signals

History
Issue Date	Notes
2024/02/dd	First documentation release

Reset scheme and control signals

The following picture shows the simplified block diagram of the reset scheme, power control signal and voltage monitoring .

AURA SOM provides the following reset signals:

• SYS_nRST, to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)
• WDOG_B, to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)

• PMIC_ON_REQ, to start a PMIC power sequence, so that reboot the SoC
• CPU_PORn, to force memories and peripherals to reset, in order to bring them in a known condition

Some releated control signals are avaible:

• SOM_PGOOD, to turn on circuitry external to the SOM
• PMIC_INTn, to manage PMIC register interrupts
• PMIC_STBY_REQ, to generate proper power for the SoC sleep mode
• ONOFF, to turn off the SoC in a low-power use cases

The electrical and functional characteristics of these signals are listed in the following table:

Signal	Type	Driven	Affect	Purpose
SYS_nRST	PMIC Input pulled-up inside the PMIC	Externally	PMIC	PMIC performs reset (cold or warm reset depends on its configuration register) when SYS_nRST is asserted low.
WDOG_B	PMIC Input pulled-up with 100 kohm inside the SOM	Externally or SoC	PMIC	PMIC performs reset (cold or warm reset depends on its configuration register) when WDOG_B is asserted low.
PMIC_ON_REQ	PMIC Input pulled-down with 100 kohm inside the SOM	Externally or SoC	PMIC	PMIC starts power on sequence when PMIC_ON_REQ is asserted high. Voltage monitors can trigger a power reset If a voltage drop occurs. This causes SoC reboot
CPU_PORn	PMIC Output, open drain pulled-up with 100 kohm inside the SOM	PMIC	SoC, onboard eMMC and PHY ETH, External	Reset memories and peripherals internal and external to the SOM after a power-on sequence. This guarantees it is in a known state when reset signal is released.
SOM_PGOOD	Monitor Output, 3V3 LVTTL	SOM	External	Turn on the external circuitry of the SOM when the SoC is ready, in order to prevent backpower.
PMIC_INTn	PMIC Output, open drain pulled-up with 10 kohm inside the SOM	PMIC	SoC and External	PMIC_INTn is asserted low when an interrupt bit status in PMIC's register is changed.
PMIC_STBY_REQ	PMIC Input pulled-down with 100 kohm inside the SOM	Externally or SoC	PMIC	PMIC enters in standby mode when PMIC_STBY_REQ is asserted high. This allows the SoC to enter sleep mode.
ONOFF	SoC Input pulled-up with 100 kohm inside the SOM	Externally	SoC	SoC enters in power down when ONOFF is asserted high. The main power must remain active so that some data can be stored even if the processor is turned off. See Battery-Backed Non-Secure Module (BBNSM) on reference manual.

Handling CPU-initiated software reset

By default, i.MX93 processor does not assert any external signal when it initiates a software reset sequence. Also, default software reset implementation does not guarantee that all processor registers are reset properly.

For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.

This technique is implemented in DESK-MX9-L. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #1 to assert the WDOG1_WDOG reset signal. This signal in turn is routed to WDOG_ANY pad (MUX mode ALT_0). At the hardware level, this signal is connected to the WDOG_B PMIC pin driving a PMIC reset.