AURA SOM/AURA Hardware/Power and Reset/Reset scheme and control signals

History
Issue Date	Notes
2024/08/08	First documentation release

Reset scheme and control signals

The following picture shows the simplified block diagram of the reset scheme, power control signals and voltage monitoring.

AURA SoM provides the following reset signals:

• SYS_nRST to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)
• WDOG_B to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)
• CPU_PORn to force memories and peripherals to reset, in order to bring them in a known condition

with some related control signals:

• SOM_PGOOD to turn on circuitry external to the SoM
• PMIC_INTn to manage PMIC register interrupts

provides this power control signal:

• ONOFF to turn the SoC off and on in case of low power use

and provides these monitor signals:

• PMIC_ON_REQ used internally to start a PMIC power sequence, so that reboot the SoC

• PMIC_STBY_REQ used internally to generate proper power for the SoC in sleep mode

The electrical and functional characteristics of these signals are listed in the following table:

Signal	Type		Driven	Affect	Purpose
SYS_nRST	Open drain, User input	PMIC Input, pulled-up inside the PMIC	Externally	PMIC	PMIC performs cold reset (warm reset can be set from configuration register) when SYS_nRST is asserted low.
WDOG_B	Open drain, User input	PMIC Input, pulled-up with 100 kohm inside the SoM	Externally or SoC	PMIC	PMIC performs cold reset (warm reset can be set from configuration register) when WDOG_B is asserted low.
CPU_PORn	Open drain, User output	PMIC Output, open drain pulled-up with 100 kohm inside the SoM	PMIC	SoC, onboard eMMC and PHY ETH, External	Reset memories and peripherals internal and external to the SoM after a power-on sequence. This guarantees it is in a known state when reset signal is released.
SOM_PGOOD	Push pull, User output	Monitor Output, 3V3 LVTTL	SoM	External	Turn on the external circuitry of the SoM when the SoC's power is ready, in order to prevent backpower.
PMIC_INTn	Open drain, User output	PMIC Output, open drain pulled-up with 10 kohm inside the SoM	PMIC	SoC and External	PMIC_INTn is asserted low when an interrupt bit status in PMIC's register is changed.
ONOFF	Open drain, User input	SoC Input, pulled-up with 100 kohm inside the SoM	Externally	SoC	SoC switches from low-power mode to run mode (or vice versa) when ONOFF is asserted low (kernel-definable modes, distinguished by short or long press). The main power must remain active so that some data can be stored even if the processor is turned off. See Battery-Backed Secure Memory (BBSM) on reference manual.
PMIC_ON_REQ	User monitor	PMIC Input, pulled-down with 100 kohm inside the SoM	SoC	PMIC	PMIC starts power on sequence when PMIC_ON_REQ is asserted high.
PMIC_STBY_REQ	User monitor	PMIC Input, pulled-down with 100 kohm inside the SoM	SoC	PMIC	PMIC enters in standby mode when PMIC_STBY_REQ is asserted high. This allows the SoC to enter sleep mode.

Handling CPU-initiated software reset

By default, i.MX93 processor does not assert any external signal when it initiates a software reset sequence. Furthermore, the default implementation of software reset, like other reset sources, initiates a complete power sequence except for the BBSM rail: all non BBSM registers are reset.

This technique is implemented in DESK-MX9-L. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #1 to assert the WDOG1_WDOG reset signal. This signal in turn is routed to WDOG_ANY pad (MUX mode ALT_0). At the hardware level, this signal is connected to the WDOG_B PMIC pin driving a PMIC reset.