AURA SOM/AURA Hardware/Power and Reset/Reset scheme and control signals

History
Issue Date	Notes
2024/02/dd	First documentation release

Reset scheme and control signals

The following picture shows the simplified block diagram of the reset scheme and voltage monitoring.

AURA SOM provides the following reset signals:

• SYS_nRST
• WDOG_B, pulled-up with 100 kohm
• CPU_PORn, pulled-up with 100 kohm. This signal, pilot by the PMIC, reset SoC's CPU and onboard eMMC and ethernet PHY.
• PMIC_INTn, pulled-up with 10 kohm

Furthermore, some control signals are avaible:

• SOM_PGOOD,

• PMIC_ON_REQ, pulled-down with 100 kohm
• PMIC_STBY_REQ, pulled-down with 100 kohm
• ONOFF, pulled-up with 100 kohm

The electrical and functional characteristics of these signals are listed in the following table:

Signal	Type	Driven	Affect	Purpose
SYS_nRST	PMIC Input pulled-up inside the PMIC	Externally	PMIC
WDOG_B	PMIC Input pulled-up with 100 kohm inside the SOM	Externally or SoC	PMIC
CPU_PORn	PMIC Output, open drain pulled-up with 100 kohm inside the SOM	PMIC	SoC, onboard eMMC and PHY ETH, External	Reset peripherals internal and external to the SOM after a power-on sequence
SOM_PGOOD	Monitor Output, 3V3 LVTTL	SOM	External	Turn on the external circuitry of the SOM
PMIC_INTn	PMIC Output, open drain pulled-up with 10 kohm inside the SOM	PMIC	SoC and External
PMIC_ON_REQ	PMIC Input pulled-down with 100 kohm inside the SOM	Externally or SoC	PMIC
PMIC_STBY_REQ	PMIC Input pulled-down with 100 kohm inside the SOM	Externally or SoC	PMIC
ONOFF	SoC Input pulled-up with 100 kohm inside the SOM	Externally	SoC

CPU_PORn

The following devices can assert this active-low signal:

• PMIC
• multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition

Since SPI NOR flash can be used as a boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.

Ciclo di reset completo utilizzare

Handling CPU-initiated software reset

By default, i.MX93 processor does not assert any external signal when it initiates a software reset sequence. Also, default software reset implementation does not guarantee that all processor registers are reset properly.

For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.

This technique is implemented in DESK-MX9-L. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #1 to assert the WDOG1_WDOG reset signal. This signal in turn is routed to WDOG_ANY pad (MUX mode ALT_0). At the hardware level, this signal is connected to the WDOG_B PMIC pin driving a PMIC reset.