Difference between revisions of "AURA SOM/AURA Hardware/Power and Reset/Reset scheme and control signals"
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| − | !colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History | + | ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History |
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| − | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date | + | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date |
| − | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes | + | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes |
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| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2024/02/dd | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |2024/02/dd |
| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First documentation release | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First documentation release |
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__FORCETOC__ | __FORCETOC__ | ||
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[[File:TBD.png | center | 400px]] | [[File:TBD.png | center | 400px]] | ||
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[[File:AURA-reset-scheme.png | 800px]] | [[File:AURA-reset-scheme.png | 800px]] | ||
| − | ''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio: | + | ''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:'' |
| − | * SYS_nRST | + | * '''SYS_nRST''' |
| − | * CPU_PORn | + | * '''CPU_PORn''', pulled-up with 100 kohm. This signal, pilot by the PMIC, reset SoC's CPU and onboard eMMC and ethernet PHY. |
| − | * | + | * '''WDOG_B''', pulled-up with 100 kohm |
| − | * | + | * '''PMIC_ON_REQ''', pulled-down with 100 kohm |
| + | * '''PMIC_STBY_REQ''', pulled-down with 100 kohm | ||
| + | * '''PMIC_INTn''', pulled-up with 10 kohm | ||
| + | * '''ONOFF''', pulled-up with 100 kohm | ||
'''TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI''' | '''TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI''' | ||
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This technique is implemented in [[DESK-MX9-L]]. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #1 to assert the WDOG1_WDOG reset signal. This signal in turn is routed to WDOG_ANY pad (MUX mode ALT_0). At the hardware level, this signal is connected to the WDOG_B PMIC pin driving a PMIC reset. | This technique is implemented in [[DESK-MX9-L]]. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #1 to assert the WDOG1_WDOG reset signal. This signal in turn is routed to WDOG_ANY pad (MUX mode ALT_0). At the hardware level, this signal is connected to the WDOG_B PMIC pin driving a PMIC reset. | ||
| − | <section end=Body/> | + | <section end="Body" /> |
[[Category:AURA]] | [[Category:AURA]] | ||
Revision as of 16:24, 12 February 2024
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Reset scheme and control signals[edit | edit source]
The following picture shows the simplified block diagram of the reset scheme and voltage monitoring.
TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:
- SYS_nRST
- CPU_PORn, pulled-up with 100 kohm. This signal, pilot by the PMIC, reset SoC's CPU and onboard eMMC and ethernet PHY.
- WDOG_B, pulled-up with 100 kohm
- PMIC_ON_REQ, pulled-down with 100 kohm
- PMIC_STBY_REQ, pulled-down with 100 kohm
- PMIC_INTn, pulled-up with 10 kohm
- ONOFF, pulled-up with 100 kohm
TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI
CPU_PORn[edit | edit source]
The following devices can assert this active-low signal:
- PMIC
- multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition
Since SPI NOR flash can be used as a boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
Handling CPU-initiated software reset[edit | edit source]
By default, i.MX93 processor does not assert any external signal when it initiates a software reset sequence. Also, default software reset implementation does not guarantee that all processor registers are reset properly.
For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
This technique is implemented in DESK-MX9-L. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #1 to assert the WDOG1_WDOG reset signal. This signal in turn is routed to WDOG_ANY pad (MUX mode ALT_0). At the hardware level, this signal is connected to the WDOG_B PMIC pin driving a PMIC reset.
