AURA SOM/AURA Hardware/Power and Reset/Reset scheme and control signals

History
Issue Date	Notes
2024/02/dd	First documentation release

Reset scheme and control signals

The following picture shows the simplified block diagram of the reset scheme and voltage monitoring.

TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:

• SYS_nRST
• CPU_PORn
• SNVS
• ...

TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI

CPU_PORn

The following devices can assert this active-low signal:

• PMIC
• multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition

Since SPI NOR flash can be used as a boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.

Handling CPU-initiated software reset

By default, i.MX93 processor does not assert any external signal when it initiates a software reset sequence. Also, default software reset implementation does not guarantee that all processor registers are reset properly.

For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.

This technique is implemented in DESK-MX9-L. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #1 to assert the WDOG1_WDOG reset signal. This signal in turn is routed to WDOG_ANY pad (MUX mode ALT_0). At the hardware level, this signal is connected to the WDOG_B PMIC pin driving a PMIC reset.