Difference between revisions of "AURA SOM/AURA Hardware/Power and Reset/Reset scheme and control signals"

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== Reset scheme and control signals ==
 
== Reset scheme and control signals ==
  
−
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
+
The following picture shows the simplified block diagram of the reset scheme and voltage monitoring.
  
 
[[File:AURA-reset-scheme.png | 800px]]
 
[[File:AURA-reset-scheme.png | 800px]]
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''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:
 
''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:
  
−
* MRST
+
* SYS_nRST
−
* POR
+
* CPU_PORn
 
* SNVS
 
* SNVS
−
* SYSRST
 
 
* ...
 
* ...
−
'''
 
  
 
'''TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI'''
 
'''TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI'''
−
 
−
''TBD: di seguito la pagina di AXEL Lite da rivedere nel caso di altri SOM''
 
−
 
−
=== PMIC_VSNVS ===
 
−
Some signals that are related to reset circuitry are pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:
 
−
* voltage applied to PMICS's VIN pin
 
−
** in case of AxelLite this pin is connected to 3.3VIN power rail
 
−
* voltage applied to PMICS's LICELL pin
 
−
** in case of AxelLite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)
 
−
* PMIC's VSNVSCTL register configuration.
 
−
Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''.
 
−
 
−
For more details please refer to section ''VSNVS LDO/Switch'' of ''MMPF0100 Advance Information'' document.
 
  
 
=== CPU_PORn ===
 
=== CPU_PORn ===
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* multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition  
 
* multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition  
  
−
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
+
Since SPI NOR flash can be used as a boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
  
  
 
=== Handling CPU-initiated software reset ===
 
=== Handling CPU-initiated software reset ===
−
'''By default, MX6 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly'''.
+
'''By default, i.MX93 processor does not assert any external signal when it initiates a software reset sequence. Also, default software reset implementation does not guarantee that all processor registers are reset properly. '''
  
 
For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
 
For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
  
−
This technique is implemented in [[DESK-MX9-L]]. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT #2 to assert the WDOG2_B reset signal. This signal in turn is routed to GPIO_1 pad (MUX mode = 1). At hardware level, this signal is AC-coupled to a 3-state output buffer (please refer to U22 chip of [[AxelEVB-Lite]] carrier board), driving PMIC_PWRON.
+
This technique is implemented in [[DESK-MX9-L]]. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #1 to assert the WDOG1_WDOG reset signal. This signal in turn is routed to WDOG_ANY pad (MUX mode ALT_0). At the hardware level, this signal is connected to the WDOG_B PMIC pin driving a PMIC reset.
  
 
<section end=Body/>
 
<section end=Body/>
  
 
[[Category:AURA]]
 
[[Category:AURA]]

Revision as of 17:17, 2 February 2024

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History
Issue Date Notes
2024/02/dd First documentation release



Reset scheme and control signals[edit | edit source]

The following picture shows the simplified block diagram of the reset scheme and voltage monitoring.

AURA-reset-scheme.png

TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:

  • SYS_nRST
  • CPU_PORn
  • SNVS
  • ...

TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI

CPU_PORn[edit | edit source]

The following devices can assert this active-low signal:

  • PMIC
  • multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition

Since SPI NOR flash can be used as a boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.


Handling CPU-initiated software reset[edit | edit source]

By default, i.MX93 processor does not assert any external signal when it initiates a software reset sequence. Also, default software reset implementation does not guarantee that all processor registers are reset properly.

For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.

This technique is implemented in DESK-MX9-L. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #1 to assert the WDOG1_WDOG reset signal. This signal in turn is routed to WDOG_ANY pad (MUX mode ALT_0). At the hardware level, this signal is connected to the WDOG_B PMIC pin driving a PMIC reset.


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