Difference between revisions of "AURA SOM/AURA Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence"

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!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |2024/02/dd
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First documentation release
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First documentation release
 
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[[File:TBD.png | center | 400px]]
 
[[File:TBD.png | center | 400px]]
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The PSU is composed of two main blocks:  
 
The PSU is composed of two main blocks:  
* power management integrated circuit
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* power management integrated circuit (PMIC)
 
* additional generic power management circuitry that completes PMIC functionalities
 
* additional generic power management circuitry that completes PMIC functionalities
  
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* generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals
 
* generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals
 
* synchronizes the powering up of carrier board to prevent back power
 
* synchronizes the powering up of carrier board to prevent back power
* provides some spare regulated voltages that can be used to power carrier board devices
 
  
 
=== Power-up sequence===
 
=== Power-up sequence===
 
The typical power-up sequence is the following:
 
The typical power-up sequence is the following:
  
* 3.3VIN main power supply rail is powered
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# VIN_SOM (+3.3V) main power supply rail is powered
* SNVS domain signals are pulled up (unless carrier board circuitry keeps this signal low for any reason)
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# CPU_PORn (active-low) is driven low by PMIC; PMIC initiates power-up sequence needed by iMX93x processor
* CPU_PORn (active-low) is driven low by PMIC
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# SOM_PGOOD goes up when all CPU, memories and I/O power rail is ready
* RTC_RESET_B are internally released after 10ms
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# CPU_PORn is released by PMIC after the last regulator is powered on; this signal bring the processor out of reset
* PMIC initiates power-up sequence needed by iMX93x processor
 
* SOM_PGOOD goes up when all CPU I/O power rail is ready
 
* CPU_PORn is de-asserted after the last regulator to bring the processor out of reset
 
  
 
==== Note on SOM_PGOOD usage ====
 
==== Note on SOM_PGOOD usage ====
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SOM_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals.  
 
SOM_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals.  
  
Depending on the kind of such loads, SOM_PGOOD might not be able to drive them properly. In these cases a simple 2-input AND port can be used to address this issue. The following picture depicts a principle schematic showing this solution.  
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Depending on the kind of such loads, SOM_PGOOD might not be able to drive them properly. On AURA SOM this signal is driven by a push-pull output at NVCC_3V3 rail, with max 20 mA current.  
  
VDD_SOM denotes the power rail used to power AURA SoM.
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[[File:AURA-power-good.png]]
 
 
 
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[[Category:AURA]]
 
[[Category:AURA]]

Revision as of 10:26, 12 February 2024

History
Issue Date Notes
2024/02/dd First documentation release



TBD.png

Power Supply Unit (PSU) and recommended power-up sequence[edit | edit source]

Implementing correct power-up sequence for i.MX93 SOC processors is not a trivial task because several power rails are involved.

AURA SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:

AURA-power-sequence.png

The PSU is composed of two main blocks:

  • power management integrated circuit (PMIC)
  • additional generic power management circuitry that completes PMIC functionalities

The PSU:

  • generates the proper power-up sequence required by the SOC processor and surrounding memories and peripherals
  • synchronizes the powering up of carrier board to prevent back power

Power-up sequence[edit | edit source]

The typical power-up sequence is the following:

  1. VIN_SOM (+3.3V) main power supply rail is powered
  2. CPU_PORn (active-low) is driven low by PMIC; PMIC initiates power-up sequence needed by iMX93x processor
  3. SOM_PGOOD goes up when all CPU, memories and I/O power rail is ready
  4. CPU_PORn is released by PMIC after the last regulator is powered on; this signal bring the processor out of reset

Note on SOM_PGOOD usage[edit | edit source]

SOM_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals.

Depending on the kind of such loads, SOM_PGOOD might not be able to drive them properly. On AURA SOM this signal is driven by a push-pull output at NVCC_3V3 rail, with max 20 mA current.