Difference between revisions of "AURA SOM/AURA Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence"
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| − | <section end=History/> | + | <section end="History" />__FORCETOC__<section begin="Body" />This page provides an overview of the issues related to powering AURA SOM. For more details about the signals that are involved, please see also [[AURA SOM/AURA Hardware/Pinout Table|this page]]. |
| − | __FORCETOC__ | ||
| − | <section begin=Body/> | ||
== Power Supply Unit (PSU) and recommended power-up sequence == | == Power Supply Unit (PSU) and recommended power-up sequence == | ||
| − | Implementing correct power-up sequence for i.MX93 | + | Implementing correct power-up sequence for i.MX93 SoC processors is not a trivial task because several power rails are involved. |
AURA SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry: | AURA SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry: | ||
| Line 22: | Line 20: | ||
The PSU is composed of two main blocks: | The PSU is composed of two main blocks: | ||
| − | * power management integrated circuit | + | * power management integrated circuit (PMIC) |
| − | * additional generic power management circuitry that completes PMIC functionalities | + | * additional generic power management circuitry that completes PMIC functionalities. |
The PSU: | The PSU: | ||
| − | * generates the proper power-up sequence required by the | + | * generates the proper power-up sequence required by the SoC, surrounding memories, and peripherals |
| − | * synchronizes the powering up of carrier board to prevent back | + | * synchronizes the powering up of carrier board's circuitry to prevent back powering. |
| − | |||
=== Power-up sequence=== | === Power-up sequence=== | ||
The typical power-up sequence is the following: | The typical power-up sequence is the following: | ||
| − | + | # VIN_SOM (+3.3V) main power supply rail is powered. | |
| − | + | # CPU_PORn (active-low) is driven low by PMIC; PMIC initiates power-up sequence needed by iMX93x processor. | |
| − | + | # SOM_PGOOD goes up when all SoC, memories, and I/O power rails are ready. | |
| − | + | # Finally PMIC releases CPU_PORn; this signal brings the processor out of reset. | |
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| − | |||
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==== Note on SOM_PGOOD usage ==== | ==== Note on SOM_PGOOD usage ==== | ||
| − | SOM_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals. | + | SOM_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals in order to prevent back power. |
| − | Depending on the kind of such loads, SOM_PGOOD might not be able to drive them properly. | + | Depending on the kind of such loads, SOM_PGOOD might not be able to drive them properly. On AURA SOM this signal is driven by a push-pull output at NVCC_3V3 rail, with max 20 mA output current. |
| − | + | ==== Note on CPU_PORn ==== | |
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| + | Internally to the SOM, CPU_PORn is pulled-up with 100 kOhm.<section end="Body" /> | ||
[[Category:AURA]] | [[Category:AURA]] | ||
Latest revision as of 15:01, 14 February 2024
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| History | |||
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| Issue Date | Notes | ||
| 2024/02/14 | First documentation release | ||
This page provides an overview of the issues related to powering AURA SOM. For more details about the signals that are involved, please see also this page.
Contents
Power Supply Unit (PSU) and recommended power-up sequence[edit | edit source]
Implementing correct power-up sequence for i.MX93 SoC processors is not a trivial task because several power rails are involved.
AURA SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
The PSU is composed of two main blocks:
- power management integrated circuit (PMIC)
- additional generic power management circuitry that completes PMIC functionalities.
The PSU:
- generates the proper power-up sequence required by the SoC, surrounding memories, and peripherals
- synchronizes the powering up of carrier board's circuitry to prevent back powering.
Power-up sequence[edit | edit source]
The typical power-up sequence is the following:
- VIN_SOM (+3.3V) main power supply rail is powered.
- CPU_PORn (active-low) is driven low by PMIC; PMIC initiates power-up sequence needed by iMX93x processor.
- SOM_PGOOD goes up when all SoC, memories, and I/O power rails are ready.
- Finally PMIC releases CPU_PORn; this signal brings the processor out of reset.
Note on SOM_PGOOD usage[edit | edit source]
SOM_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals in order to prevent back power.
Depending on the kind of such loads, SOM_PGOOD might not be able to drive them properly. On AURA SOM this signal is driven by a push-pull output at NVCC_3V3 rail, with max 20 mA output current.
Note on CPU_PORn[edit | edit source]
Internally to the SOM, CPU_PORn is pulled-up with 100 kOhm.
