Difference between revisions of "AURA SOM/AURA Hardware/Peripherals/LCD"

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==Peripheral LCD ==
 
==Peripheral LCD ==
  
''TBD: sostituire le sezioni con le informazioni sull'uso della periferica''
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The LCD interface available on AURA is based on i.Mx93 SoC and fetches graphics stored in memory and display them on a TFT LCD panel.
''Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMI''
 
  
 
=== Description  ===
 
=== Description  ===
  
The LCD interface available on AURA is based on xxxxx ''TBD:SOC name'' SoC.
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The LCD port supports the following standards and features:
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* Parallel display (up to 1366x768 or 1280x800)
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* The display mode supports DOTCLK mode only
 +
• One layer can support the programmable plane size(Width/Height/Pitch) on the panel
  
The LCD port supports the following standards and features:
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The LCD interface may be driven by a Pixel Processing Pipeline (PXP) used to process graphics buffers or composite video and graphics data before sending to an LCD display.
  
* High-Definition Multimedia Interface Specification, Version 1.4a
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The PXP combines the following into a single processing engine:
* Support for up to 1080p at 60Hz HDTV display resolutions and up to QXGA graphic display resolutions.
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* Scaling: YUV 422, 420, 444 and any RGB formatted pixels
* Support for 4k x 2k and 3D video formats
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* Color Space Conversion (CSC): converting from YUV to RGB
* Support for up to 16-bit Deep Color modes
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* Secondary Color Space Conversion (CSC2)
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* Rotation: 0, 90, 180, 270 degrees and vertical/horizontal flips
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* Composite Alpha Blending and Color Key
  
 
===Pin mapping===
 
===Pin mapping===

Latest revision as of 09:20, 13 September 2023

History
Issue Date Notes
2023/09/13 First release



Peripheral LCD[edit | edit source]

The LCD interface available on AURA is based on i.Mx93 SoC and fetches graphics stored in memory and display them on a TFT LCD panel.

Description[edit | edit source]

The LCD port supports the following standards and features:

  • Parallel display (up to 1366x768 or 1280x800)
  • The display mode supports DOTCLK mode only

• One layer can support the programmable plane size(Width/Height/Pitch) on the panel

The LCD interface may be driven by a Pixel Processing Pipeline (PXP) used to process graphics buffers or composite video and graphics data before sending to an LCD display.

The PXP combines the following into a single processing engine:

  • Scaling: YUV 422, 420, 444 and any RGB formatted pixels
  • Color Space Conversion (CSC): converting from YUV to RGB
  • Secondary Color Space Conversion (CSC2)
  • Rotation: 0, 90, 180, 270 degrees and vertical/horizontal flips
  • Composite Alpha Blending and Color Key

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section