AURA SOM/AURA Hardware/Peripherals/LCD

History
Issue Date	Notes
2023/09/13	First release
2025/06/12	Add LCD pin mapping table

Peripheral LCD

The LCD interface available on AURA is based on i.Mx93 SoC and fetches graphics stored in memory and display them on a TFT LCD panel.

Description

The LCD port supports the following standards and features:

• Parallel display (up to 1366x768 or 1280x800)
• The display mode supports DOTCLK mode only

• One layer can support the programmable plane size(Width/Height/Pitch) on the panel

The LCD interface may be driven by a Pixel Processing Pipeline (PXP) used to process graphics buffers or composite video and graphics data before sending to an LCD display.

The PXP combines the following into a single processing engine:

• Scaling: YUV 422, 420, 444 and any RGB formatted pixels
• Color Space Conversion (CSC): converting from YUV to RGB
• Secondary Color Space Conversion (CSC2)
• Rotation: 0, 90, 180, 270 degrees and vertical/horizontal flips
• Composite Alpha Blending and Color Key

Pin mapping

The Pin mapping is described in the Pinout table section

LCD pins table mapping

The following table lists the LCD interface pads mapped to the AURA SO-DIMM pads:

LCD signal	IO PAD	SO-DIMM pin	Notes
PCLK	GPIO_IO00	179
DE	GPIO_IO01	183
VSYNC	GPIO_IO02	195
HSYNC	GPIO_IO03	181
D[0]	GPIO_IO04	80
D[1]	GPIO_IO05	78
D[2]	GPIO_IO06	43
D[3]	GPIO_IO07	40
D[4]	GPIO_IO08	49
D[5]	GPIO_IO09	47
D[6]	GPIO_IO10	55
D[7]	GPIO_IO11	59
D[8]	GPIO_IO12	191
D[9]	GPIO_IO13	193
D[10]	GPIO_IO14	89
D[11]	GPIO_IO15	91
D[12]	GPIO_IO16	66
D[13]	GPIO_IO17	34
D[14]	GPIO_IO18	45
D[15]	GPIO_IO19	68
D[16]	GPIO_IO20	72
D[17]	GPIO_IO21	36
D[18]	GPIO_IO22	74
D[19]	GPIO_IO23	76
D[20]	GPIO_IO24	46
D[21]	GPIO_IO25	42
D[22]	GPIO_IO26	70
D[23]	GPIO_IO27	44