Difference between revisions of "AURA SOM/AURA Hardware/Peripherals/SPI"

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==Peripheral SPI ==
 
==Peripheral SPI ==
  
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''TBD: sostituire le sezioni con le informazioni sull'uso della periferica''
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A SPI bus is a synchronous serial communication interface used in embedded systems. It is typically used to perform short-distance communications between microcontrollers and peripheral devices.
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''Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMI''
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The SPI interface available on AURA is based on i.MX93 SoC. The chip includes eight instances of LPSPI Modules:
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* LPSPI1 and LPSPI2 are in ''Low Power Real Time Domain''
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* LPSPI[3..8] are in ''Application Flex Domain''
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* SPI1 and SPI2 are only supported in Master Mode, not Slave Mode.
  
 
=== Description  ===
 
=== Description  ===
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The SPI interface available on AURA is based on xxxxx ''TBD:SOC name'' SoC.
 
  
 
The SPI port supports the following standards and features:
 
The SPI port supports the following standards and features:
  
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* High-Definition Multimedia Interface Specification, Version 1.4a
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* FIFO register access supported by DMA transmit and receive requests
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* Support for up to 1080p at 60Hz HDTV display resolutions and up to QXGA graphic display resolutions.
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* Continues operating in Stop mode, if configured to do so and an appropriate clock is available
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* Support for 4k x 2k and 3D video formats
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* 32-bit word size
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* Support for up to 16-bit Deep Color modes
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* Configurable clock polarity and phase
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* Master mode—supports 2 peripheral chip selects and Slave mode
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* 8-word transmit, receive and command FIFO
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* Flexible timing parameters in Master mode, including SCK frequency and duty cycle, and delays between PCS and SCK edges
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* Continuous transfer option to keep PCS asserted across multiple frames
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* Full-duplex transfers support 1-bit transmit and receive on each clock edge and Half-duplex transfers support
  
 
===Pin mapping===
 
===Pin mapping===

Latest revision as of 11:16, 13 September 2023

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History
Issue Date Notes
2023/09/13 First release



Peripheral SPI[edit | edit source]

A SPI bus is a synchronous serial communication interface used in embedded systems. It is typically used to perform short-distance communications between microcontrollers and peripheral devices.

The SPI interface available on AURA is based on i.MX93 SoC. The chip includes eight instances of LPSPI Modules:

  • LPSPI1 and LPSPI2 are in Low Power Real Time Domain
  • LPSPI[3..8] are in Application Flex Domain
  • SPI1 and SPI2 are only supported in Master Mode, not Slave Mode.

Description[edit | edit source]

The SPI port supports the following standards and features:

  • FIFO register access supported by DMA transmit and receive requests
  • Continues operating in Stop mode, if configured to do so and an appropriate clock is available
  • 32-bit word size
  • Configurable clock polarity and phase
  • Master mode—supports 2 peripheral chip selects and Slave mode
  • 8-word transmit, receive and command FIFO
  • Flexible timing parameters in Master mode, including SCK frequency and duty cycle, and delays between PCS and SCK edges
  • Continuous transfer option to keep PCS asserted across multiple frames
  • Full-duplex transfers support 1-bit transmit and receive on each clock edge and Half-duplex transfers support

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section

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